mirror of https://github.com/YosysHQ/nextpnr.git
wip
This commit is contained in:
Miodrag Milanovic
parent
f67113f399
commit
130f32da5c
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@ -912,10 +912,10 @@ X(D0_01)
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X(D1_01)
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X(D0_10)
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X(D1_10)
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X(M1)
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X(M2)
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X(M3)
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X(M4)
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X(IN1)
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X(IN2)
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X(IN3)
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X(IN4)
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X(OUT)
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X(CPOUT)
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@ -946,10 +946,10 @@ X(CPE_LT_L)
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//X(D0_10)
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//X(D1_10)
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X(COMBIN)
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//X(M1)
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//X(M2)
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//X(M3)
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//X(M4)
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//X(IN1)
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//X(IN2)
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//X(IN3)
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//X(IN4)
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//X(OUT)
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//X(CPOUT)
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@ -973,10 +973,10 @@ X(CPE_RAMIO_L)
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// hardware primitive CPE_BRIDGE
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X(CPE_BRIDGE)
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// CPE_BRIDGE pins
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X(IN1)
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X(IN2)
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X(IN3)
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X(IN4)
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//X(IN1)
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//X(IN2)
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//X(IN3)
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//X(IN4)
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X(IN5)
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X(IN6)
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X(IN7)
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@ -986,6 +986,18 @@ X(MUXOUT)
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// hardware primitive CPE_LT_FULL
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X(CPE_LT_FULL)
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// CPE_LT_FULL pins
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//X(D0_00)
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//X(D1_00)
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//X(D0_01)
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//X(D1_01)
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X(D0_02)
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X(D1_02)
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X(D0_03)
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X(D1_03)
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//X(D0_10)
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//X(D1_10)
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X(D0_11)
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X(D1_11)
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//X(IN1)
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//X(IN2)
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//X(IN3)
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@ -449,7 +449,7 @@ void GateMateImpl::postRoute()
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log_info("Check CPEs..\n");
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dict<IdString,int> cfg;
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dict<IdString,IdString> port_mapping;
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auto add_input = [&](IdString orig_port, IdString port) {
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auto add_input = [&](IdString orig_port, IdString port, bool merged) {
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static dict<IdString,IdString> convert_port = {
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{ctx->id("CPE.IN1"),id_IN1},
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{ctx->id("CPE.IN2"),id_IN2},
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@ -463,13 +463,26 @@ void GateMateImpl::postRoute()
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{ctx->id("CPE.CINX"),id_CINX},
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{ctx->id("CPE.PINX"),id_PINX}
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};
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static dict<IdString,IdString> convert_port_merged = {
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{ctx->id("CPE.IN1"),id_IN1},
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{ctx->id("CPE.IN2"),id_IN2},
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{ctx->id("CPE.IN3"),id_IN3},
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{ctx->id("CPE.IN4"),id_IN4},
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{ctx->id("CPE.IN5"),id_IN5},
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{ctx->id("CPE.IN6"),id_IN6},
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{ctx->id("CPE.IN7"),id_IN7},
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{ctx->id("CPE.IN8"),id_IN8},
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{ctx->id("CPE.PINY1"),id_PINY1},
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{ctx->id("CPE.CINX"),id_CINX},
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{ctx->id("CPE.PINX"),id_PINX}
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};
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if (convert_port.count(port)) {
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//printf("CONVERTED %s %s\n",orig_port.c_str(ctx), port.c_str(ctx));
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port_mapping.emplace(orig_port, convert_port[port]);
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port_mapping.emplace(orig_port, merged ? convert_port_merged[port] : convert_port[port]);
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};
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};
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auto check_input = [&](CellInfo *cell, IdString port) {
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auto check_input = [&](CellInfo *cell, IdString port, bool merged) {
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if (cell->getPort(port)) {
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NetInfo *net = cell->getPort(port);
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WireId pin_wire = ctx->getBelPinWire(cell->bel, port);
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@ -483,7 +496,7 @@ void GateMateImpl::postRoute()
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if (extra_data.type == PipExtra::PIP_EXTRA_MUX) {
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//printf("name:%s %d\n",IdString(extra_data.name).c_str(ctx),extra_data.value);
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cfg.emplace(IdString(extra_data.name),extra_data.value);
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add_input(port, ctx->getWireName(src)[1]);
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add_input(port, ctx->getWireName(src)[1], merged);
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}
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if (net->wires.count(src)) {
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@ -496,7 +509,7 @@ void GateMateImpl::postRoute()
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if (extra_data.type == PipExtra::PIP_EXTRA_MUX) {
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//printf("name:%s %d\n",IdString(extra_data.name).c_str(ctx),extra_data.value);
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cfg.emplace(IdString(extra_data.name),extra_data.value);
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add_input(port, ctx->getWireName(src)[1]);
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add_input(port, ctx->getWireName(src)[1], merged);
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}
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@ -510,7 +523,7 @@ void GateMateImpl::postRoute()
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if (extra_data.type == PipExtra::PIP_EXTRA_MUX) {
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//printf("name:%s %d\n",IdString(extra_data.name).c_str(ctx),extra_data.value);
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cfg.emplace(IdString(extra_data.name),extra_data.value);
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add_input(port, ctx->getWireName(src)[1]);
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add_input(port, ctx->getWireName(src)[1], merged);
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}
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} else {
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@ -545,12 +558,12 @@ void GateMateImpl::postRoute()
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//printf("L00 %04b\n",l00);
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//printf("L01 %04b\n",l01);
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//printf("L10 %04b\n",l10);
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check_input(cell.second.get(), id_D0_00);
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check_input(cell.second.get(), id_D1_00);
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check_input(cell.second.get(), id_D0_01);
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check_input(cell.second.get(), id_D1_01);
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check_input(cell.second.get(), id_D0_10);
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check_input(cell.second.get(), id_D1_10);
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check_input(cell.second.get(), id_D0_00, false);
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check_input(cell.second.get(), id_D1_00, false);
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check_input(cell.second.get(), id_D0_01, false);
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check_input(cell.second.get(), id_D1_01, false);
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check_input(cell.second.get(), id_D0_10, false);
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check_input(cell.second.get(), id_D1_10, false);
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if (cfg.count(ctx->id("LUT2_11")) || cfg.count(ctx->id("LUT2_10"))) {
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//printf("LUT2 like\n");
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if (cfg.count(ctx->id("LUT2_11"))) { //lower
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@ -648,6 +661,64 @@ void GateMateImpl::postRoute()
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cell.second->params[id_C_I4] = Property(1,1);
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}
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if (cell.second->type.in(id_CPE_MX4)) {
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//printf("\n");
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cfg.clear();
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port_mapping.clear();
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//printf("type:%s name:%s\n",cell.second->type.c_str(ctx),cell.second->name.c_str(ctx));
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int l00 = int_or_default(cell.second->params, id_INIT_L00, 0);
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int l01 = int_or_default(cell.second->params, id_INIT_L01, 0);
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//int l10 = int_or_default(cell.second->params, id_INIT_L10, 0);
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int l02 = int_or_default(cell.second->params, id_INIT_L02, 0);
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int l03 = int_or_default(cell.second->params, id_INIT_L03, 0);
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//int l11 = int_or_default(cell.second->params, id_INIT_L11, 0);
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//printf("L00 %04b\n",l00);
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//printf("L01 %04b\n",l01);
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//printf("L10 %04b\n",l10);
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check_input(cell.second.get(), id_D0_00, true);
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check_input(cell.second.get(), id_D1_00, true);
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check_input(cell.second.get(), id_D0_01, true);
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check_input(cell.second.get(), id_D1_01, true);
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check_input(cell.second.get(), id_D0_02, true);
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check_input(cell.second.get(), id_D1_02, true);
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check_input(cell.second.get(), id_D0_03, true);
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check_input(cell.second.get(), id_D1_03, true);
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//check_input(cell.second.get(), id_D0_10);
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//check_input(cell.second.get(), id_D1_10);
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//check_input(cell.second.get(), id_D0_11);
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//check_input(cell.second.get(), id_D1_11);
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if (cfg.count(ctx->id("LUT2_00")) && cfg.at(ctx->id("LUT2_00"))==1) {
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l00 = swap_lut2_inputs(l00);
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}
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if (cfg.count(ctx->id("LUT2_01")) && cfg.at(ctx->id("LUT2_01"))==1) {
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l01 = swap_lut2_inputs(l01);
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}
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if (cfg.count(ctx->id("LUT2_02")) && cfg.at(ctx->id("LUT2_02"))==1) {
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l02 = swap_lut2_inputs(l02);
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}
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if (cfg.count(ctx->id("LUT2_03")) && cfg.at(ctx->id("LUT2_03"))==1) {
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l03 = swap_lut2_inputs(l03);
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}
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cell.second->params[id_INIT_L00] = Property(l00,4);
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cell.second->params[id_INIT_L01] = Property(l01,4);
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cell.second->params[id_INIT_L02] = Property(l02,4);
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cell.second->params[id_INIT_L03] = Property(l03,4);
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//cell.second->params[id_INIT_L10] = Property(l10,4);
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//cell.second->params[id_INIT_L11] = Property(l11,4);
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cell.second->renamePort(id_D0_00, port_mapping[id_D0_00]);
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cell.second->renamePort(id_D1_00, port_mapping[id_D1_00]);
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cell.second->renamePort(id_D0_01, port_mapping[id_D0_01]);
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cell.second->renamePort(id_D1_01, port_mapping[id_D1_01]);
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cell.second->renamePort(id_D0_02, port_mapping[id_D0_02]);
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cell.second->renamePort(id_D1_02, port_mapping[id_D1_02]);
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cell.second->renamePort(id_D0_03, port_mapping[id_D0_03]);
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cell.second->renamePort(id_D1_03, port_mapping[id_D1_03]);
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}
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}
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ctx->assignArchInfo();
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@ -373,6 +373,14 @@ void GateMatePacker::repack_cpe()
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loc.z = CPE_LT_FULL_Z;
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ctx->unbindBel(bel);
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ctx->bindBel(ctx->getBelByLocation(loc), cell.second.get(), strength);
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cell.second->renamePort(id_D0_00, id_D0_02);
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cell.second->renamePort(id_D1_00, id_D1_02);
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cell.second->renamePort(id_D0_01, id_D0_03);
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cell.second->renamePort(id_D1_01, id_D1_03);
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cell.second->renamePort(id_D0_10, id_D0_11);
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cell.second->renamePort(id_D1_10, id_D1_11);
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cell.second->renamePort(id_IN1, id_IN5);
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cell.second->renamePort(id_IN2, id_IN6);
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cell.second->renamePort(id_IN3, id_IN7);
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@ -423,6 +431,14 @@ void GateMatePacker::repack_cpe()
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cell.second->params[id_C_I1] = Property(int_or_default(upper->params, id_C_I1, 0), 1);
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if (upper->params.count(id_C_I2))
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cell.second->params[id_C_I2] = Property(int_or_default(upper->params, id_C_I2, 0), 1);
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upper->movePortTo(id_D0_00, cell.second.get(), id_D0_00);
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upper->movePortTo(id_D1_00, cell.second.get(), id_D1_00);
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upper->movePortTo(id_D0_01, cell.second.get(), id_D0_01);
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upper->movePortTo(id_D1_01, cell.second.get(), id_D1_01);
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upper->movePortTo(id_D0_10, cell.second.get(), id_D0_10);
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upper->movePortTo(id_D1_10, cell.second.get(), id_D1_10);
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upper->movePortTo(id_IN1, cell.second.get(), id_IN1);
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upper->movePortTo(id_IN2, cell.second.get(), id_IN2);
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upper->movePortTo(id_IN3, cell.second.get(), id_IN3);
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@ -327,8 +327,8 @@ void GateMatePacker::pack_cpe()
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ci.cluster = ci.name;
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ci.renamePort(id_Y, id_OUT);
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ci.renamePort(id_S0, id_D1_00); // IN6
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ci.renamePort(id_S1, id_D1_01); // IN8
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ci.renamePort(id_S0, id_D0_00); // IN5
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ci.renamePort(id_S1, id_D0_01); // IN7
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uint8_t select = 0;
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uint8_t invert = 0;
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@ -346,8 +346,8 @@ void GateMatePacker::pack_cpe()
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}
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}
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ci.params[id_C_FUNCTION] = Property(C_MX4, 3);
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ci.params[id_INIT_L02] = Property(LUT_D1, 4); // IN6
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ci.params[id_INIT_L03] = Property(LUT_D1, 4); // IN8
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ci.params[id_INIT_L02] = Property(LUT_D0, 4); // IN5
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ci.params[id_INIT_L03] = Property(LUT_D0, 4); // IN7
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ci.params[id_INIT_L11] = Property(invert, 4); // Inversion bits
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ci.params[id_INIT_L20] = Property(LUT_D1, 4); // Always D1
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ci.type = id_CPE_LT_L;
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@ -360,10 +360,10 @@ void GateMatePacker::pack_cpe()
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upper->params[id_INIT_L10] = Property(select, 4); // Selection bits
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upper->params[id_C_FUNCTION] = Property(C_MX4, 3);
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ci.movePortTo(id_D0, upper, id_M1);
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ci.movePortTo(id_D1, upper, id_M2);
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ci.movePortTo(id_D2, upper, id_M3);
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ci.movePortTo(id_D3, upper, id_M4);
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ci.movePortTo(id_D0, upper, id_IN1);
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ci.movePortTo(id_D1, upper, id_IN2);
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ci.movePortTo(id_D2, upper, id_IN3);
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ci.movePortTo(id_D3, upper, id_IN4);
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ci.constr_children.push_back(upper);
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NetInfo *o = ci.getPort(id_OUT);
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