From 130f32da5c331812bc1441ec2ca3cb5398c2b5d8 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 4 Dec 2025 08:00:49 +0100 Subject: [PATCH] wip --- himbaechel/uarch/gatemate/constids.inc | 36 ++++++---- himbaechel/uarch/gatemate/gatemate.cc | 95 ++++++++++++++++++++++---- himbaechel/uarch/gatemate/pack.cc | 16 +++++ himbaechel/uarch/gatemate/pack_cpe.cc | 16 ++--- 4 files changed, 131 insertions(+), 32 deletions(-) diff --git a/himbaechel/uarch/gatemate/constids.inc b/himbaechel/uarch/gatemate/constids.inc index 34062954..89dc20cd 100644 --- a/himbaechel/uarch/gatemate/constids.inc +++ b/himbaechel/uarch/gatemate/constids.inc @@ -912,10 +912,10 @@ X(D0_01) X(D1_01) X(D0_10) X(D1_10) -X(M1) -X(M2) -X(M3) -X(M4) +X(IN1) +X(IN2) +X(IN3) +X(IN4) X(OUT) X(CPOUT) @@ -946,10 +946,10 @@ X(CPE_LT_L) //X(D0_10) //X(D1_10) X(COMBIN) -//X(M1) -//X(M2) -//X(M3) -//X(M4) +//X(IN1) +//X(IN2) +//X(IN3) +//X(IN4) //X(OUT) //X(CPOUT) @@ -973,10 +973,10 @@ X(CPE_RAMIO_L) // hardware primitive CPE_BRIDGE X(CPE_BRIDGE) // CPE_BRIDGE pins -X(IN1) -X(IN2) -X(IN3) -X(IN4) +//X(IN1) +//X(IN2) +//X(IN3) +//X(IN4) X(IN5) X(IN6) X(IN7) @@ -986,6 +986,18 @@ X(MUXOUT) // hardware primitive CPE_LT_FULL X(CPE_LT_FULL) // CPE_LT_FULL pins +//X(D0_00) +//X(D1_00) +//X(D0_01) +//X(D1_01) +X(D0_02) +X(D1_02) +X(D0_03) +X(D1_03) +//X(D0_10) +//X(D1_10) +X(D0_11) +X(D1_11) //X(IN1) //X(IN2) //X(IN3) diff --git a/himbaechel/uarch/gatemate/gatemate.cc b/himbaechel/uarch/gatemate/gatemate.cc index 80ce0109..fbf260d9 100644 --- a/himbaechel/uarch/gatemate/gatemate.cc +++ b/himbaechel/uarch/gatemate/gatemate.cc @@ -449,7 +449,7 @@ void GateMateImpl::postRoute() log_info("Check CPEs..\n"); dict cfg; dict port_mapping; - auto add_input = [&](IdString orig_port, IdString port) { + auto add_input = [&](IdString orig_port, IdString port, bool merged) { static dict convert_port = { {ctx->id("CPE.IN1"),id_IN1}, {ctx->id("CPE.IN2"),id_IN2}, @@ -463,13 +463,26 @@ void GateMateImpl::postRoute() {ctx->id("CPE.CINX"),id_CINX}, {ctx->id("CPE.PINX"),id_PINX} }; + static dict convert_port_merged = { + {ctx->id("CPE.IN1"),id_IN1}, + {ctx->id("CPE.IN2"),id_IN2}, + {ctx->id("CPE.IN3"),id_IN3}, + {ctx->id("CPE.IN4"),id_IN4}, + {ctx->id("CPE.IN5"),id_IN5}, + {ctx->id("CPE.IN6"),id_IN6}, + {ctx->id("CPE.IN7"),id_IN7}, + {ctx->id("CPE.IN8"),id_IN8}, + {ctx->id("CPE.PINY1"),id_PINY1}, + {ctx->id("CPE.CINX"),id_CINX}, + {ctx->id("CPE.PINX"),id_PINX} + }; if (convert_port.count(port)) { //printf("CONVERTED %s %s\n",orig_port.c_str(ctx), port.c_str(ctx)); - port_mapping.emplace(orig_port, convert_port[port]); + port_mapping.emplace(orig_port, merged ? convert_port_merged[port] : convert_port[port]); }; }; - auto check_input = [&](CellInfo *cell, IdString port) { + auto check_input = [&](CellInfo *cell, IdString port, bool merged) { if (cell->getPort(port)) { NetInfo *net = cell->getPort(port); WireId pin_wire = ctx->getBelPinWire(cell->bel, port); @@ -483,7 +496,7 @@ void GateMateImpl::postRoute() if (extra_data.type == PipExtra::PIP_EXTRA_MUX) { //printf("name:%s %d\n",IdString(extra_data.name).c_str(ctx),extra_data.value); cfg.emplace(IdString(extra_data.name),extra_data.value); - add_input(port, ctx->getWireName(src)[1]); + add_input(port, ctx->getWireName(src)[1], merged); } if (net->wires.count(src)) { @@ -496,7 +509,7 @@ void GateMateImpl::postRoute() if (extra_data.type == PipExtra::PIP_EXTRA_MUX) { //printf("name:%s %d\n",IdString(extra_data.name).c_str(ctx),extra_data.value); cfg.emplace(IdString(extra_data.name),extra_data.value); - add_input(port, ctx->getWireName(src)[1]); + add_input(port, ctx->getWireName(src)[1], merged); } @@ -510,7 +523,7 @@ void GateMateImpl::postRoute() if (extra_data.type == PipExtra::PIP_EXTRA_MUX) { //printf("name:%s %d\n",IdString(extra_data.name).c_str(ctx),extra_data.value); cfg.emplace(IdString(extra_data.name),extra_data.value); - add_input(port, ctx->getWireName(src)[1]); + add_input(port, ctx->getWireName(src)[1], merged); } } else { @@ -545,12 +558,12 @@ void GateMateImpl::postRoute() //printf("L00 %04b\n",l00); //printf("L01 %04b\n",l01); //printf("L10 %04b\n",l10); - check_input(cell.second.get(), id_D0_00); - check_input(cell.second.get(), id_D1_00); - check_input(cell.second.get(), id_D0_01); - check_input(cell.second.get(), id_D1_01); - check_input(cell.second.get(), id_D0_10); - check_input(cell.second.get(), id_D1_10); + check_input(cell.second.get(), id_D0_00, false); + check_input(cell.second.get(), id_D1_00, false); + check_input(cell.second.get(), id_D0_01, false); + check_input(cell.second.get(), id_D1_01, false); + check_input(cell.second.get(), id_D0_10, false); + check_input(cell.second.get(), id_D1_10, false); if (cfg.count(ctx->id("LUT2_11")) || cfg.count(ctx->id("LUT2_10"))) { //printf("LUT2 like\n"); if (cfg.count(ctx->id("LUT2_11"))) { //lower @@ -648,6 +661,64 @@ void GateMateImpl::postRoute() cell.second->params[id_C_I4] = Property(1,1); } + if (cell.second->type.in(id_CPE_MX4)) { + //printf("\n"); + cfg.clear(); + port_mapping.clear(); + //printf("type:%s name:%s\n",cell.second->type.c_str(ctx),cell.second->name.c_str(ctx)); + int l00 = int_or_default(cell.second->params, id_INIT_L00, 0); + int l01 = int_or_default(cell.second->params, id_INIT_L01, 0); + //int l10 = int_or_default(cell.second->params, id_INIT_L10, 0); + int l02 = int_or_default(cell.second->params, id_INIT_L02, 0); + int l03 = int_or_default(cell.second->params, id_INIT_L03, 0); + //int l11 = int_or_default(cell.second->params, id_INIT_L11, 0); + //printf("L00 %04b\n",l00); + //printf("L01 %04b\n",l01); + //printf("L10 %04b\n",l10); + check_input(cell.second.get(), id_D0_00, true); + check_input(cell.second.get(), id_D1_00, true); + check_input(cell.second.get(), id_D0_01, true); + check_input(cell.second.get(), id_D1_01, true); + check_input(cell.second.get(), id_D0_02, true); + check_input(cell.second.get(), id_D1_02, true); + check_input(cell.second.get(), id_D0_03, true); + check_input(cell.second.get(), id_D1_03, true); + + //check_input(cell.second.get(), id_D0_10); + //check_input(cell.second.get(), id_D1_10); + //check_input(cell.second.get(), id_D0_11); + //check_input(cell.second.get(), id_D1_11); + + + if (cfg.count(ctx->id("LUT2_00")) && cfg.at(ctx->id("LUT2_00"))==1) { + l00 = swap_lut2_inputs(l00); + } + if (cfg.count(ctx->id("LUT2_01")) && cfg.at(ctx->id("LUT2_01"))==1) { + l01 = swap_lut2_inputs(l01); + } + if (cfg.count(ctx->id("LUT2_02")) && cfg.at(ctx->id("LUT2_02"))==1) { + l02 = swap_lut2_inputs(l02); + } + if (cfg.count(ctx->id("LUT2_03")) && cfg.at(ctx->id("LUT2_03"))==1) { + l03 = swap_lut2_inputs(l03); + } + + cell.second->params[id_INIT_L00] = Property(l00,4); + cell.second->params[id_INIT_L01] = Property(l01,4); + cell.second->params[id_INIT_L02] = Property(l02,4); + cell.second->params[id_INIT_L03] = Property(l03,4); + //cell.second->params[id_INIT_L10] = Property(l10,4); + //cell.second->params[id_INIT_L11] = Property(l11,4); + + cell.second->renamePort(id_D0_00, port_mapping[id_D0_00]); + cell.second->renamePort(id_D1_00, port_mapping[id_D1_00]); + cell.second->renamePort(id_D0_01, port_mapping[id_D0_01]); + cell.second->renamePort(id_D1_01, port_mapping[id_D1_01]); + cell.second->renamePort(id_D0_02, port_mapping[id_D0_02]); + cell.second->renamePort(id_D1_02, port_mapping[id_D1_02]); + cell.second->renamePort(id_D0_03, port_mapping[id_D0_03]); + cell.second->renamePort(id_D1_03, port_mapping[id_D1_03]); + } } ctx->assignArchInfo(); diff --git a/himbaechel/uarch/gatemate/pack.cc b/himbaechel/uarch/gatemate/pack.cc index 52289e2d..44c4661b 100644 --- a/himbaechel/uarch/gatemate/pack.cc +++ b/himbaechel/uarch/gatemate/pack.cc @@ -373,6 +373,14 @@ void GateMatePacker::repack_cpe() loc.z = CPE_LT_FULL_Z; ctx->unbindBel(bel); ctx->bindBel(ctx->getBelByLocation(loc), cell.second.get(), strength); + cell.second->renamePort(id_D0_00, id_D0_02); + cell.second->renamePort(id_D1_00, id_D1_02); + cell.second->renamePort(id_D0_01, id_D0_03); + cell.second->renamePort(id_D1_01, id_D1_03); + cell.second->renamePort(id_D0_10, id_D0_11); + cell.second->renamePort(id_D1_10, id_D1_11); + + cell.second->renamePort(id_IN1, id_IN5); cell.second->renamePort(id_IN2, id_IN6); cell.second->renamePort(id_IN3, id_IN7); @@ -423,6 +431,14 @@ void GateMatePacker::repack_cpe() cell.second->params[id_C_I1] = Property(int_or_default(upper->params, id_C_I1, 0), 1); if (upper->params.count(id_C_I2)) cell.second->params[id_C_I2] = Property(int_or_default(upper->params, id_C_I2, 0), 1); + + upper->movePortTo(id_D0_00, cell.second.get(), id_D0_00); + upper->movePortTo(id_D1_00, cell.second.get(), id_D1_00); + upper->movePortTo(id_D0_01, cell.second.get(), id_D0_01); + upper->movePortTo(id_D1_01, cell.second.get(), id_D1_01); + upper->movePortTo(id_D0_10, cell.second.get(), id_D0_10); + upper->movePortTo(id_D1_10, cell.second.get(), id_D1_10); + upper->movePortTo(id_IN1, cell.second.get(), id_IN1); upper->movePortTo(id_IN2, cell.second.get(), id_IN2); upper->movePortTo(id_IN3, cell.second.get(), id_IN3); diff --git a/himbaechel/uarch/gatemate/pack_cpe.cc b/himbaechel/uarch/gatemate/pack_cpe.cc index a0315590..cddf0103 100644 --- a/himbaechel/uarch/gatemate/pack_cpe.cc +++ b/himbaechel/uarch/gatemate/pack_cpe.cc @@ -327,8 +327,8 @@ void GateMatePacker::pack_cpe() ci.cluster = ci.name; ci.renamePort(id_Y, id_OUT); - ci.renamePort(id_S0, id_D1_00); // IN6 - ci.renamePort(id_S1, id_D1_01); // IN8 + ci.renamePort(id_S0, id_D0_00); // IN5 + ci.renamePort(id_S1, id_D0_01); // IN7 uint8_t select = 0; uint8_t invert = 0; @@ -346,8 +346,8 @@ void GateMatePacker::pack_cpe() } } ci.params[id_C_FUNCTION] = Property(C_MX4, 3); - ci.params[id_INIT_L02] = Property(LUT_D1, 4); // IN6 - ci.params[id_INIT_L03] = Property(LUT_D1, 4); // IN8 + ci.params[id_INIT_L02] = Property(LUT_D0, 4); // IN5 + ci.params[id_INIT_L03] = Property(LUT_D0, 4); // IN7 ci.params[id_INIT_L11] = Property(invert, 4); // Inversion bits ci.params[id_INIT_L20] = Property(LUT_D1, 4); // Always D1 ci.type = id_CPE_LT_L; @@ -360,10 +360,10 @@ void GateMatePacker::pack_cpe() upper->params[id_INIT_L10] = Property(select, 4); // Selection bits upper->params[id_C_FUNCTION] = Property(C_MX4, 3); - ci.movePortTo(id_D0, upper, id_M1); - ci.movePortTo(id_D1, upper, id_M2); - ci.movePortTo(id_D2, upper, id_M3); - ci.movePortTo(id_D3, upper, id_M4); + ci.movePortTo(id_D0, upper, id_IN1); + ci.movePortTo(id_D1, upper, id_IN2); + ci.movePortTo(id_D2, upper, id_IN3); + ci.movePortTo(id_D3, upper, id_IN4); ci.constr_children.push_back(upper); NetInfo *o = ci.getPort(id_OUT);