From 0d913b2eb9ad44aeb58289410489d92bd4c0931b Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sun, 22 Jun 2025 18:58:40 +0200
Subject: [PATCH] Fixes

---
 himbaechel/uarch/gatemate/bitstream.cc    | 3 ---
 himbaechel/uarch/gatemate/gatemate.cc     | 1 +
 himbaechel/uarch/gatemate/gen/arch_gen.py | 8 +++++++-
 himbaechel/uarch/gatemate/pack_cpe.cc     | 2 +-
 4 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/himbaechel/uarch/gatemate/bitstream.cc b/himbaechel/uarch/gatemate/bitstream.cc
index 14e4c42f..4e8a6858 100644
--- a/himbaechel/uarch/gatemate/bitstream.cc
+++ b/himbaechel/uarch/gatemate/bitstream.cc
@@ -243,13 +243,10 @@ struct BitstreamBackend
                 break;
             case id_CPE_L2T4.index:
             case id_CPE_L2T5.index:
-            case id_CPE_L2T5_U.index:
-            case id_CPE_L2T5_L.index:
             case id_CPE_FF.index:
             case id_CPE_RAMI.index:
             case id_CPE_RAMO.index:
             case id_CPE_RAMIO.index:
-            case id_CPE_LT.index:
             case id_CPE_LT_U.index:
             case id_CPE_LT_L.index: {
                 // Update configuration bits based on signal inversion
diff --git a/himbaechel/uarch/gatemate/gatemate.cc b/himbaechel/uarch/gatemate/gatemate.cc
index a57424fe..4520caa0 100644
--- a/himbaechel/uarch/gatemate/gatemate.cc
+++ b/himbaechel/uarch/gatemate/gatemate.cc
@@ -252,6 +252,7 @@ void GateMateImpl::postPlace()
         for (auto &port : ctx->cells[pcell]->ports) {
             ctx->cells[pcell]->disconnectPort(port.first);
         }
+        ctx->unbindBel(ctx->cells[pcell]->bel);
         ctx->cells.erase(pcell);
     }
     delete_cells.clear();
diff --git a/himbaechel/uarch/gatemate/gen/arch_gen.py b/himbaechel/uarch/gatemate/gen/arch_gen.py
index 821b24ed..21ec462f 100644
--- a/himbaechel/uarch/gatemate/gen/arch_gen.py
+++ b/himbaechel/uarch/gatemate/gen/arch_gen.py
@@ -172,8 +172,14 @@ def set_timings(ch):
     dff.add_setup_hold("CLK", "DIN", ClockEdge.RISING, TimingValue(60), TimingValue(50))
     dff.add_clock_out("CLK", "DOUT", ClockEdge.RISING, TimingValue(60))
 
+    lut = ch.timing.add_cell_variant(speed, "CPE_RAMI")
+    lut.add_comb_arc("RAM_I", "OUT", TimingValue(0, 0))
+
+    lut = ch.timing.add_cell_variant(speed, "CPE_RAMO")
+    lut.add_comb_arc("I", "RAM_O", TimingValue(0, 0))
+
     lut = ch.timing.add_cell_variant(speed, "CPE_RAMIO")
-    lut.add_comb_arc("I", "OUT", TimingValue(0, 0))
+    #lut.add_comb_arc("I", "OUT", TimingValue(0, 0))
     lut.add_comb_arc("I", "RAM_O", TimingValue(0, 0))
     lut.add_comb_arc("RAM_I", "OUT", TimingValue(0, 0))
 
diff --git a/himbaechel/uarch/gatemate/pack_cpe.cc b/himbaechel/uarch/gatemate/pack_cpe.cc
index d49a972b..7fec79f0 100644
--- a/himbaechel/uarch/gatemate/pack_cpe.cc
+++ b/himbaechel/uarch/gatemate/pack_cpe.cc
@@ -272,7 +272,7 @@ void GateMatePacker::pack_cpe()
     }
     for (auto &cell : dff_list) {
         CellInfo &ci = *cell;
-        CellInfo *lt = create_cell_ptr(id_CPE_LT, ctx->idf("%s$lt", ci.name.c_str(ctx)));
+        CellInfo *lt = create_cell_ptr(id_CPE_L2T4, ctx->idf("%s$lt", ci.name.c_str(ctx)));
         lt->cluster = ci.name;
         lt->constr_abs_z = false;
         lt->constr_z = -2;