mirror of
https://github.com/RTimothyEdwards/netgen.git
synced 2026-08-28 17:05:45 +02:00
Tim Edwards
4d65b0006d
some problems stemming from comparing a case-sensitive netlist
against a case-insensitive one. Verilog netlist reading does
not yet have support for macros other than "`include", and it
does not yet have support for bit vectors constructed with
braces ({}).
17 lines
462 B
Makefile
17 lines
462 B
Makefile
MODULE = base
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NETGENDIR = ..
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SRCS = actel.c ccode.c greedy.c ntk.c print.c actellib.c embed.c \
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hash.c netfile.c objlist.c query.c anneal.c ext.c netcmp.c netgen.c \
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pdutils.c random.c timing.c bottomup.c flatten.c place.c spice.c \
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verilog.c wombat.c xilinx.c xillib.c
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X11_SRCS = xnetgen.c
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include ${NETGENDIR}/defs.mak
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SRCS += ${GR_SRCS}
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DFLAGS += ${GR_DFLAGS}
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DFLAGS += -DNETGEN_DATE="\"`date`\""
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CFLAGS += ${GR_CFLAGS}
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include ${NETGENDIR}/rules.mak
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