Files
netgen/base
Tim Edwards e821381900 Corrected a rather obscure error in which an otherwise unconnected
port-to-port short (formed by "assign" in verilog or zero-valued
resistors in SPICE) does not get checked when counting nodes
before adding a proxy pin to a subcircuit in that cell, causing
the proxy pin to be assigned the same node number and forming an
unintended connection to the port-to-port connecting net.
2024-09-30 22:11:53 -04:00
..
2023-02-28 09:02:41 -05:00
2024-01-03 21:21:03 -05:00
2021-11-17 11:53:04 -05:00
2023-02-28 09:02:41 -05:00