Merge branch 'master' into netgen-1.5

from Mitch Bailey.

.github/workflows/main.yml

@@ -0,0 +1,40 @@
+# This is a basic workflow to help you get started with Actions
+
+name: CI
+
+# Controls when the workflow will run
+on:
+  # Triggers the workflow on push or pull request events but only for the master branch
+  push:
+    branches: [ master ]
+  pull_request:
+    branches: [ master ]
+
+  # Allows you to run this workflow manually from the Actions tab
+  workflow_dispatch:
+
+# A workflow run is made up of one or more jobs that can run sequentially or in parallel
+jobs:
+  # This workflow contains a single job called "build"
+  build:
+    # The type of runner that the job will run on
+    runs-on: ubuntu-latest
+
+    # Steps represent a sequence of tasks that will be executed as part of the job
+    steps:
+      # Runs a set of commands using the runners shell
+      #- name: Logging into Dockerhub
+      #  run: docker login -u ${{ secrets.DOCKERHUB_USERNAME }} -p ${{ secrets.DOCKERHUB_PASSWORD }}
+        
+      - name: Pulling the docker image
+        run: docker pull vezzal/vezzal:v1
+        
+      - name: Start the container with the docker image
+        run: docker run -id --name test_netgen vezzal/vezzal:v1 bash | exit
+        
+      - name: Run the testing on the container and send the mail
+        run: docker exec test_netgen /vezzal/test_netgen.sh "[email protected],[email protected]" ${{ secrets.MAILING_KEY }}
+        
+  
+      
+          

README.md

@@ -1,4 +1,8 @@
-NETGEN:  VERSION 1.5
+![Continuous Integration](https://github.com/RTimothyEdwards/netgen/actions/workflows/main.yml/badge.svg)
+
+# NETGEN
+
+### VERSION 1.5
 
 NETGEN is a general-purpose netlist management system.  It can read
 and write several netlist formats, including NTK (Caltech, CMU),

VERSION

@@ -1 +1 @@
-1.5.192
+1.5.202

base/netcmp.c

@@ -4121,6 +4121,7 @@ void series_sort(struct objlist *ob1, struct nlist *tp1, int idx1, int run)
    sval = 1;
    cval = slop = 0.0;
    for (i = 0; i < run; i++) {
+      sl = NULL;
       merge_type = MERGE_NONE;
       for (p = 0;; p++) {
 	 vl = &(obp->instance.props[p]);
@@ -4149,13 +4150,13 @@ void series_sort(struct objlist *ob1, struct nlist *tp1, int idx1, int run)
 	 proplist[i].value = cval * (double)sval;
          proplist[i].slop = slop;
          proplist[i].avalue = 0;
-	 sl->value.ival = 1;
+	 if (sl) sl->value.ival = 1;
       }
       else if (merge_type == MERGE_S_PAR) {
 	 proplist[i].value = cval / (double)sval;
          proplist[i].slop = slop;
          proplist[i].avalue = 0;
-	 sl->value.ival = 1;
+	 if (sl) sl->value.ival = 1;
       }
       else {
 	 /* Components which declare no series addition method stay unsorted */
@@ -6891,11 +6892,6 @@ int reorderpins(struct hashlist *p, int file)
 		"Ordering will be arbitrary.\n", tc2->name);
 
     for (ob = ptr->cell; ob != NULL; ) {
-        /* Catch badness */
-	if (ob->next && (ob->next->node > 100000)) {
-	    Fprintf(stdout, "Bad.\n");
-	} 
-
 	if (ob->type == FIRSTPIN) {
 	    if ((*matchfunc)(ob->model.class, tc2->name)) {
 		char *sptr = ob->instance.name;
@@ -7343,35 +7339,44 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
    /* so apply only to black-box (CELL_PLACEHOLDER) entries.	*/ 
    /* (Semi-hack: Allow "!" global flag) */
 
-   if (((tc1->flags & CELL_PLACEHOLDER) && (tc2->flags & CELL_PLACEHOLDER)) ||
-	    (NodeClasses == NULL)) {
-      ob1 = tc1->cell;
-      bangptr1 = strrchr(ob1->name, '!');
-      if (bangptr1 && (*(bangptr1 + 1) == '\0'))
-         *bangptr1 = '\0';
-      else bangptr1 = NULL;
+   ob1 = tc1->cell;
+   bangptr1 = strrchr(ob1->name, '!');
+   if (bangptr1 && (*(bangptr1 + 1) == '\0'))
+      *bangptr1 = '\0';
+   else bangptr1 = NULL;
   
-      for (i = 0; i < numorig; i++) {
-         if (*(cover + i) == (char)0) {
-	    j = 0;
-            for (ob2 = tc2->cell; ob2 != NULL; ob2 = ob2->next) {
-	       char *name1, *name2;
+   for (i = 0; i < numorig; i++) {
+      if (*(cover + i) == (char)0) {
+	 j = 0;
+         for (ob2 = tc2->cell; ob2 != NULL; ob2 = ob2->next) {
+	    char *name1, *name2;
 
-	       if (!IsPort(ob2)) break;
+	    if (!IsPort(ob2)) break;
 
-	       bangptr2 = strrchr(ob2->name, '!');
-	       if (bangptr2 && (*(bangptr2 + 1) == '\0'))
-	          *bangptr2 = '\0';
-	       else bangptr2 = NULL;
+	    bangptr2 = strrchr(ob2->name, '!');
+	    if (bangptr2 && (*(bangptr2 + 1) == '\0'))
+	       *bangptr2 = '\0';
+	    else bangptr2 = NULL;
 
-	       name1 = ob1->name;
-	       name2 = ob2->name;
+	    name1 = ob1->name;
+	    name2 = ob2->name;
 
-	       /* Recognize proxy pins as matching */
-	       if (!strncmp(name1, "proxy", 5)) name1 +=5;
-	       if (!strncmp(name2, "proxy", 5)) name2 +=5;
+	    /* Recognize proxy pins as matching unconnected pins */
+	    if (!strncmp(name1, "proxy", 5) && (ob2->node == -1)) name1 +=5;
+	    if (!strncmp(name2, "proxy", 5) && (ob1->node == -1)) name2 +=5;
+
+	    if ((*matchfunc)(name1, name2)) {
+
+	       /* If both sides have unconnected nodes, then pins with	*/
+	       /* matching names are an automatic match.  Otherwise, if	*/
+	       /* matching black-box entries, then pins are always	*/
+	       /* matched by name.					*/
+
+	       if (((ob1->node == -1) && (ob2->node == -1)) ||
+			(((tc1->flags & CELL_PLACEHOLDER) &&
+			(tc2->flags & CELL_PLACEHOLDER)) ||
+			(NodeClasses == NULL))) {
 
-	       if ((*matchfunc)(name1, name2)) {
 	          ob2->model.port = i;		/* save order */
 	          *(cover + i) = (char)1;
 
@@ -7398,13 +7403,15 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
 				Tcl_NewStringObj(ob2->name, -1));
 	          }
 #endif
+	          if (bangptr2) *bangptr2 = '!';
+		  break;
 	       }
-	       if (bangptr2) *bangptr2 = '!';
-	       j++;
 	    }
+	    if (bangptr2) *bangptr2 = '!';
+	    j++;
          }
-         ob1 = ob1->next;
       }
+      ob1 = ob1->next;
       if (bangptr1) *bangptr1 = '!';
    }
 
@@ -7456,6 +7463,12 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
 	 if ((obt == NULL) && (notempty == 1)) {
 	    ob2->node = -2;	// Will run this through cleanuppins
 	    needclean2 = 1;
+
+	    /* On the top level, missing pins are an error, even if	*/
+	    /* they appear to match unconnected pins on the other side. */
+	    if (CompareQueue == NULL)
+		result = 0;
+
 #ifdef TCL_NETGEN
             if (dolist) {
 	       Tcl_ListObjAppendElement(netgeninterp, plist1,
@@ -7543,7 +7556,8 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
       }
 
       if (ob1 == NULL || ob1->type != PORT || ob1->node >= 0
-		|| (ob1->node < 0 && tc1->class == CLASS_MODULE)) {
+		|| (ob1->node < 0 && tc1->class == CLASS_MODULE)
+		|| (ob1->node < 0 && ob1->model.port == -1)) {
 
 	 /* Add a proxy pin to tc2 */
          obn = (struct objlist *)CALLOC(1, sizeof(struct objlist));
@@ -7560,8 +7574,7 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
          obn->instance.name = NULL;
          obn->node = -1;
 
-#if 0
-	 /* Note:  This pin has already been accounted for */
+	 /* Note:  Has this pin already been accounted for? */
 	 if (Debug == 0) {
 	    if (strcmp(ob1->name, "(no pins)")) {
 	       for (m = 0; m < left_col_end; m++) *(ostr + m) = ' ';
@@ -7577,7 +7590,6 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
 	    Fprintf(stderr, "No netlist match for cell %s pin %s\n",
 				tc1->name, ob1->name);
 	 }
-#endif
 
 	 if (ob2 == tc2->cell) {
 	    obn->next = ob2;

base/verilog.c

@@ -1577,6 +1577,14 @@ nextinst:
 		     }
 		     new_port->net = wire_bundle;
 		  }
+		  else if (nexttok[0] == '~' || nexttok[0] == '!' || nexttok[0] == '-') {
+		     /* All of these imply that the signal is logically manipulated */
+		     /* in turn implying behavioral code.			    */
+		     Printf("Module '%s' is not structural verilog, "
+				    "making black-box.\n", model);
+		     SetClass(CLASS_MODULE);
+		     goto skip_endmodule;
+		  }
 		  else
 		     new_port->net = strsave(nexttok);
 

python/Makefile

@@ -29,6 +29,7 @@ lvs_manager.py: lvs_manager.py.in
 $(DESTDIR)${INSTALL_PYDIR}/lvs_manager.py: lvs_manager.py
 	${RM} $@
 	${CP} lvs_manager.py $@
+	chmod a+x $@
 
 $(DESTDIR)${INSTALL_PYDIR}/treeviewsplit.py: treeviewsplit.py
 	${RM} $@

tcltk/netgen.tcl.in

@@ -532,7 +532,7 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
    }
    set properr {}
    set matcherr {}
-   set pinsgood 0
+   set pinsgood -1
    while {$endval != {}} {
       if {$dolist == 1} {
          netgen::run -list converge
@@ -562,11 +562,11 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
             if {[netgen::print queue] != {}} {
 	       if {([lsearch $noflat [lindex $endval 0]] == -1) &&
 			([lsearch $noflat [lindex $endval 1]] == -1)} {
-	           netgen::log put "  Flattening non-matched subcircuits $endval"
+	           netgen::log put "  Flattening non-matched subcircuits $endval\n"
 	           netgen::flatten class "[lindex $endval 0] $fnum1"
 	           netgen::flatten class "[lindex $endval 1] $fnum2"
 	       } else {
-	           netgen::log put "  Continuing with black-boxed subcircuits $endval"
+	           netgen::log put "  Continuing with black-boxed subcircuits $endval\n"
 		   lappend matcherr [lindex $endval 0]
 	           # Match pins
                    netgen::log echo off
@@ -586,7 +586,6 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
 	       }
 	    }
 	 } else {
-	    # Match pins
             netgen::log echo off
 	    if {$dolist == 1} {
 		set result [equate -list pins "$fnum1 [lindex $endval 0]" \
@@ -599,7 +598,11 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
 		equate classes "$fnum1 [lindex $endval 0]" \
 			 "$fnum2 [lindex $endval 1]"
 	    }
-	    set pinsgood $result
+	    # If $uresult == -1 then these are black-box entries and
+	    # $pinsgood should not be set to the resulting value.
+	    if {$uresult > 0} {
+	        set pinsgood $result
+	    }
             netgen::log echo on
 	 }
 	 if {$uresult == 2} {lappend properr [lindex $endval 0]}
@@ -608,13 +611,13 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
          if {[netgen::print queue] != {}} {
 	    if {([lsearch $noflat [lindex $endval 1]] == -1) &&
 		    ([lsearch $noflat [lindex $endval 1]] == -1)} {
-	       netgen::log put "  Flattening non-matched subcircuits $endval"
+	       netgen::log put "  Flattening non-matched subcircuits $endval\n"
 	       netgen::flatten class "[lindex $endval 0] $fnum1"
 	       netgen::flatten class "[lindex $endval 1] $fnum2"
 	    } else {
-	       netgen::log put "  Continuing with black-boxed subcircuits $endval"
+	       netgen::log put "  Continuing with black-boxed subcircuits $endval\n"
 	       lappend matcherr [lindex $endval 0]
-	       netgen::log put "  Continuing with black-boxed subcircuits $endval"
+	       netgen::log put "  Continuing with black-boxed subcircuits $endval\n"
 	       lappend matcherr [lindex $endval 0]
 	       # Match pins
                netgen::log echo off
@@ -647,7 +650,8 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
    puts stdout "Result: " nonewline
    netgen::log echo on
    if {$pinsgood == 0} {
-      netgen::log put "The top level cell failed pin matching.\n"
+      # NOTE:  Need to disambiguate these two cases. . .
+      netgen::log put "Cells failed matching, or top level cell failed pin matching.\n"
    } else {
       verify only
    }