verilog parser. The parser should now be able to handle any
conditionals anywhere in the verilog code. Also a bug was found
in the code that handles "a = b" assignments, and corrected.
code using the backtick expression. Also expanded the parsing of
"ifdef", "ifndef", and "endif" to include "elsif" and "else". All
forms of "if" statements should now be handled, since verilog does
not define boolean expressions in ifdef operators like most languages
do.
perfect). Given the complexities of the verilog language, the simple
strtok() tokenizer used by the SPICE parser is not sufficient. Wrote
a better tokenizer that can distinguish between whitespace and
functional tokens like parentheses, semicolons, etc., which are tokens
themselves but also token separators.
some problems stemming from comparing a case-sensitive netlist
against a case-insensitive one. Verilog netlist reading does
not yet have support for macros other than "`include", and it
does not yet have support for bit vectors constructed with
braces ({}).
Tim Edwards