netgen

Commit Graph

Author	SHA1	Message	Date
Tim Edwards	aee4b846e2	Corrected the known issue with pin bus index matching that was in the last commit and which was expected to be corrected by this commit.	2018-04-16 17:19:26 -04:00
Tim Edwards	58d7e17231	Corrected basic problem with verilog instance pins not needing to be in any specific order since all ports are named. Also corrected problem with pin names not using the same string matching function as used for nets in general (which affects the ability to match against different bus delimiters).	2018-04-16 15:41:20 -04:00
Tim Edwards	4d65b0006d	Added new handling for verilog structural netlists, and fixed some problems stemming from comparing a case-sensitive netlist against a case-insensitive one. Verilog netlist reading does not yet have support for macros other than "`include", and it does not yet have support for bit vectors constructed with braces ({}).	2018-04-12 17:09:10 -04:00

Author

SHA1

Message

Date

Tim Edwards

aee4b846e2

Corrected the known issue with pin bus index matching that was in

the last commit and which was expected to be corrected by this
commit.

2018-04-16 17:19:26 -04:00

Tim Edwards

58d7e17231

Corrected basic problem with verilog instance pins not needing to

be in any specific order since all ports are named.  Also corrected
problem with pin names not using the same string matching function
as used for nets in general (which affects the ability to match
against different bus delimiters).

2018-04-16 15:41:20 -04:00

Tim Edwards

4d65b0006d

Added new handling for verilog structural netlists, and fixed

some problems stemming from comparing a case-sensitive netlist
against a case-insensitive one.  Verilog netlist reading does
not yet have support for macros other than "`include", and it
does not yet have support for bit vectors constructed with
braces ({}).

2018-04-12 17:09:10 -04:00

3 Commits