netgen

Commit Graph

Author	SHA1	Message	Date
Tim Edwards	3a03e769af	Substantially improved verilog parsing (although almost certainly not perfect). Given the complexities of the verilog language, the simple strtok() tokenizer used by the SPICE parser is not sufficient. Wrote a better tokenizer that can distinguish between whitespace and functional tokens like parentheses, semicolons, etc., which are tokens themselves but also token separators.	2018-09-24 15:09:29 -04:00
Tim Edwards	4d65b0006d	Added new handling for verilog structural netlists, and fixed some problems stemming from comparing a case-sensitive netlist against a case-insensitive one. Verilog netlist reading does not yet have support for macros other than "`include", and it does not yet have support for bit vectors constructed with braces ({}).	2018-04-12 17:09:10 -04:00
Tim Edwards	d5e9f81cb0	Initial commit at Mon May 18 09:27:46 EDT 2015 by tim on stravinsky	2015-05-18 09:27:46 -04:00

Author

SHA1

Message

Date

Tim Edwards

3a03e769af

Substantially improved verilog parsing (although almost certainly not

perfect).  Given the complexities of the verilog language, the simple
strtok() tokenizer used by the SPICE parser is not sufficient.  Wrote
a better tokenizer that can distinguish between whitespace and
functional tokens like parentheses, semicolons, etc., which are tokens
themselves but also token separators.

2018-09-24 15:09:29 -04:00

Tim Edwards

4d65b0006d

Added new handling for verilog structural netlists, and fixed

some problems stemming from comparing a case-sensitive netlist
against a case-insensitive one.  Verilog netlist reading does
not yet have support for macros other than "`include", and it
does not yet have support for bit vectors constructed with
braces ({}).

2018-04-12 17:09:10 -04:00

Tim Edwards

d5e9f81cb0

Initial commit at Mon May 18 09:27:46 EDT 2015 by tim on stravinsky

2015-05-18 09:27:46 -04:00

3 Commits