luke
/
netgen
mirror of https://github.com/RTimothyEdwards/netgen.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
231 Commits 3 Branches 268 Tags 4 MiB
Commit Graph

2 Commits

Author SHA1 Message Date
Tim Edwards 4d65b0006d Added new handling for verilog structural netlists, and fixed 
some problems stemming from comparing a case-sensitive netlist
against a case-insensitive one.  Verilog netlist reading does
not yet have support for macros other than "`include", and it
does not yet have support for bit vectors constructed with
braces ({}).
 2018-04-12 17:09:10 -04:00
Tim Edwards d5e9f81cb0 Initial commit at Mon May 18 09:27:46 EDT 2015 by tim on stravinsky 2015-05-18 09:27:46 -04:00