Corrected the verilog parser for handling parameters and parameters
with increment/decrement syntax at the end. Also the parser now handles additional keywords associated with behavioral verilog (initial, specify) and flags modules with them as black-box entries.
This commit is contained in:
Tim Edwards
parent
f04c72b984
commit
f12d03fcff
199
base/verilog.c
199
base/verilog.c
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@ -123,6 +123,17 @@ int GetBusTok(struct bus *wb)
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result = sscanf(nexttok, "%d", &start);
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if (result != 1) {
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char *aptr = NULL;
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char addin;
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// Check for "+/-(n)" at end of a parameter name
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aptr = strrchr(nexttok, '+');
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if (aptr == NULL) aptr = strrchr(nexttok, '-');
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if (aptr != NULL) {
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addin = *aptr;
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*aptr = '\0';
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}
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// Is name in the parameter list?
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kl = (struct property *)HashLookup(nexttok, &verilogparams);
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if (kl == NULL) {
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@ -156,6 +167,15 @@ int GetBusTok(struct bus *wb)
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return 1;
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}
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}
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if (aptr != NULL) {
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int addval;
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*aptr = addin;
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if (sscanf(aptr + 1, "%d", &addval) != 1) {
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Printf("Unable to parse parameter increment '%s'\n", aptr);
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return 1;
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}
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start += (addin == '+') ? addval : -addval;
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}
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}
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SkipTokComments(VLOG_DELIMITERS);
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if (match(nexttok, "]")) {
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@ -171,6 +191,17 @@ int GetBusTok(struct bus *wb)
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result = sscanf(nexttok, "%d", &end);
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if (result != 1) {
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char *aptr = NULL;
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char addin;
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// Check for "+/-(n)" at end of a parameter name
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aptr = strrchr(nexttok, '+');
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if (aptr == NULL) aptr = strrchr(nexttok, '-');
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if (aptr != NULL) {
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addin = *aptr;
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*aptr = '\0';
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}
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// Is name in the parameter list?
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kl = (struct property *)HashLookup(nexttok, &verilogparams);
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if (kl == NULL) {
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@ -205,6 +236,15 @@ int GetBusTok(struct bus *wb)
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return 1;
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}
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}
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if (aptr != NULL) {
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int addval;
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*aptr = addin;
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if (sscanf(aptr + 1, "%d", &addval) != 1) {
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Printf("Unable to parse parameter increment '%s'\n", aptr);
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return 1;
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}
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end += (addin == '+') ? addval : -addval;
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}
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}
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}
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wb->start = start;
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@ -585,6 +625,81 @@ void ReadVerilogFile(char *fname, int filenum, struct cellstack **CellStackPtr,
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}
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}
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/* Handle parameters by treating as a localparam or definition. */
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/* Currently anything other than a constant value is not handled */
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/* and so will flag a warning. */
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else if (match(nexttok, "parameter") || match(nexttok, "localparam")) {
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char *paramkey = NULL;
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char *paramval = NULL;
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// Pick up key = value pairs and store in current cell. Look only
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// at the keyword before "=". Then set the defition as everything
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// remaining in the line, excluding comments, until the end-of-statement
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while (nexttok != NULL)
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{
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struct property *kl = NULL;
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/* Parse for parameters used in expressions. Save */
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/* parameters in the "verilogparams" hash table. */
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SkipTok(VLOG_DELIMITERS);
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if ((nexttok == NULL) || (nexttok[0] == '\0')) break;
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if (match(nexttok, "=")) {
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/* Pick up remainder of statement */
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while (nexttok != NULL) {
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SkipTokNoNewline("X///**/X;,");
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if (nexttok == NULL) break;
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if (match(nexttok, ";") || match(nexttok, ",")) break;
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if (paramval == NULL) paramval = strsave(nexttok);
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else {
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char *paramlast;
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/* Append nexttok to paramval */
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paramlast = paramval;
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paramval = (char *)MALLOC(strlen(paramlast) + strlen(nexttok)
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+ 2);
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sprintf(paramval, "%s %s", paramlast, nexttok);
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FREE(paramlast);
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}
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}
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kl = NewProperty();
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kl->key = strsave(paramkey);
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kl->idx = 0;
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kl->merge = MERGE_NONE;
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if (ConvertStringToInteger(paramval, &ival) == 1) {
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kl->type = PROP_INTEGER;
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kl->slop.ival = 0;
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kl->pdefault.ival = ival;
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}
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else if (ConvertStringToFloat(paramval, &dval) == 1) {
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kl->type = PROP_DOUBLE;
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kl->slop.dval = 0.01;
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kl->pdefault.dval = dval;
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}
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else {
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kl->type = PROP_STRING;
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kl->slop.dval = 0.0;
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kl->pdefault.string = strsave(paramval);
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}
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HashPtrInstall(paramkey, kl, &verilogparams);
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FREE(paramval);
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paramval = NULL;
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if ((nexttok == NULL) || match(nexttok, ";")) break;
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}
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else {
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if (paramkey != NULL) FREE(paramkey);
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paramkey = strsave(nexttok);
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}
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}
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if (paramval != NULL) FREE(paramval);
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if (paramkey != NULL) FREE(paramkey);
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}
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else if (match(nexttok, "module")) {
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InitializeHashTable(&buses, OBJHASHSIZE);
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SkipTokNoNewline(VLOG_DELIMITERS);
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@ -979,44 +1094,13 @@ skip_endmodule:
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}
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/* Presumably it is not an error to undefine an undefined keyword */
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}
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else if (match(nexttok, "localparam")) {
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// Pick up key = value pairs and store in current cell
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while (nexttok != NULL)
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{
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struct property *kl = NULL;
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/* Parse for parameters used in expressions. Save */
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/* parameters in the "verilogparams" hash table. */
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SkipTokNoNewline(VLOG_DELIMITERS);
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if ((nexttok == NULL) || (nexttok[0] == '\0')) break;
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if ((eqptr = strchr(nexttok, '=')) != NULL) {
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*eqptr = '\0';
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kl = NewProperty();
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kl->key = strsave(nexttok);
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kl->idx = 0;
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kl->merge = MERGE_NONE;
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if (ConvertStringToInteger(eqptr + 1, &ival) == 1) {
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kl->type = PROP_INTEGER;
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kl->slop.ival = 0;
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kl->pdefault.ival = ival;
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else if (match(nexttok, "real") || match(nexttok, "integer")) {
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Printf("Ignoring '%s' in module '%s'\n", nexttok, model);
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/* Do not skip to end of module, as these can be in the middle of */
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/* I/O assignments, which need to be parsed. */
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while (!match(nexttok, ";")) SkipTok("X///**/X,;");
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continue;
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}
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else if (ConvertStringToFloat(eqptr + 1, &dval) == 1) {
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kl->type = PROP_DOUBLE;
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kl->slop.dval = 0.01;
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kl->pdefault.dval = dval;
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}
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else {
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kl->type = PROP_STRING;
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kl->slop.dval = 0.0;
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kl->pdefault.string = strsave(eqptr + 1);
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}
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HashPtrInstall(nexttok, kl, &verilogparams);
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}
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}
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}
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else if (match(nexttok, "wire") || match(nexttok, "assign")) { /* wire = node */
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struct bus wb, wb2, *nb;
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char nodename[128], noderoot[100];
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@ -1204,7 +1288,9 @@ skip_endmodule:
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// Ignore any other directive starting with a backtick (e.g., `timescale)
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SkipNewLine(VLOG_DELIMITERS);
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}
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else if (match(nexttok, "reg") || match(nexttok, "always")) {
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else if (match(nexttok, "reg") || match(nexttok, "always") ||
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match(nexttok, "specify") || match(nexttok, "initial")) {
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Printf("Behavioral keyword '%s' found in source.\n", nexttok);
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Printf("Module '%s' is not structural verilog, making black-box.\n", model);
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// To be done: Remove any contents (but may not be necessary)
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// Recast as module
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@ -1214,6 +1300,7 @@ skip_endmodule:
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else { /* module instances */
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char instancename[100], modulename[100];
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int itype, arraystart, arrayend, arraymax, arraymin;
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char ignore;
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instancename[99] = '\0';
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modulename[99] = '\0';
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@ -1233,9 +1320,12 @@ skip_endmodule:
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PushStack(fname, CellStackPtr);
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}
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SkipTokComments(VLOG_DELIMITERS);
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nextinst:
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ignore = FALSE;
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head = NULL;
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tail = NULL;
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SkipTokComments(VLOG_DELIMITERS);
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// Next token must be '#(' (parameters) or an instance name
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@ -1308,19 +1398,21 @@ skip_endmodule:
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// Read the pin list
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while (nexttok != NULL) {
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SkipTokComments(VLOG_DELIMITERS);
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// NOTE: Deal with `ifdef et al. properly. Ignoring for now.
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while (nexttok[0] == '`') {
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SkipNewLine(VLOG_DELIMITERS);
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SkipTokComments(VLOG_DELIMITERS);
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}
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if (match(nexttok, ")")) break;
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else if (match(nexttok, ",")) continue;
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// We need to look for pins of the type ".name(value)"
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if (nexttok[0] != '.') {
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Printf("Badly formed subcircuit pin line at \"%s\"\n", nexttok);
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SkipNewLine(VLOG_DELIMITERS);
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Printf("Warning: Ignoring subcircuit with no pin names "
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"at \"%s\"\n", nexttok);
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InputParseError(stderr);
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while (nexttok != NULL) {
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SkipTokComments(VLOG_DELIMITERS);
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if (match(nexttok, ";")) break;
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}
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ignore = TRUE;
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break;
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}
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else {
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new_port = (struct portelement *)CALLOC(1, sizeof(struct portelement));
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@ -1401,10 +1493,21 @@ skip_endmodule:
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else {
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Printf("Expected to find instance pin block but got \"%s\"\n", nexttok);
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}
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/* Instance should end with a semicolon */
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if (ignore == TRUE) continue; /* moving along. . . */
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/* Verilog allows multiple instances of a single cell type to be chained */
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/* together with commas. */
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SkipTokComments(VLOG_DELIMITERS);
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if (!match(nexttok, ";")) {
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if (match(nexttok, ",")) {
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goto nextinst;
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}
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/* Otherwise, instance must end with a semicolon */
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else if (!match(nexttok, ";")) {
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Printf("Expected to find end of instance but got \"%s\"\n", nexttok);
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InputParseError(stderr);
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}
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/* Check for ignored class */
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