From f04c72b9844aee7fbe635c94a676ef1818969d43 Mon Sep 17 00:00:00 2001 From: Tim Edwards Date: Tue, 10 Sep 2019 10:52:15 -0400 Subject: [PATCH] Corrected missing case (greater-than or equal instead of greater than) that affects vectors sliced across instance arrays. Can cause vector numbers to be out-of-bounds if an instance is arrayed but each instance is listed separately. --- base/verilog.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/base/verilog.c b/base/verilog.c index 7635d51..a9da3e3 100644 --- a/base/verilog.c +++ b/base/verilog.c @@ -1752,7 +1752,7 @@ skip_endmodule: // Instance must be an array char netname[128]; int slice; - if (wb.start > wb.end && arraystart > arrayend) + if (wb.start >= wb.end && arraystart >= arrayend) slice = wb.start - (arraystart - i); else if (wb.start < wb.end && arraystart > arrayend) slice = wb.start + (arraystart - i); @@ -1760,6 +1760,7 @@ skip_endmodule: slice = wb.start - (arraystart + i); else // (wb.start < wb.end && arraystart < arrayend) slice = wb.start + (arraystart + i); + sprintf(netname, "%s[%d]", scanroot, slice); if (LookupObject(netname, CurrentCell) == NULL) Node(netname); join(netname, obptr->name);