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Merge branch 'master' into netgen-1.5

This commit is contained in:
Tim Edwards 2021-12-27 03:00:18 -05:00
parent 8ed4e3cf38 a026d37f11
commit c25c4e1160
3 changed files with 8 additions and 6 deletions
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2
VERSION
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@ -1 +1 @@
1.5.213 1.5.214

10
base/query.c
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@ -805,11 +805,13 @@ void DescribeInstance(char *name, int file)
/* All black-box modules and placeholders by definition have all */ /* All black-box modules and placeholders by definition have all */
/* disconnected pins, so don't report those. */ /* disconnected pins, so don't report those. */
if ((!(tp->flags & CELL_PLACEHOLDER)) && (tp->class != CLASS_MODULE)) if ((!(tp->flags & CELL_PLACEHOLDER)) && (tp->class != CLASS_MODULE)) {
{ // if (disconnectednodes == 0) Fprintf(stderr, "\n");
//if (disconnectednodes == 0) Fprintf(stderr, "\n");
disconnectednodes++; disconnectednodes++;
Fprintf(stderr, "Cell %s(%d) disconnected node: %s\n", tp->name, tp->file, ob->name); /* Don't report on ports marked "port_match_error", which is just confusing. */
if (strcmp(ob->name, "port_match_error")) {
Fprintf(stderr, "Cell %s(%d) disconnected node: %s\n", tp->name, tp->file, ob->name);
}
} }
} }
} }

2
base/verilog.c
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@ -2117,7 +2117,7 @@ nextinst:
sobj = sobj->next) { sobj = sobj->next) {
if (sobj->type == FIRSTPIN) { if (sobj->type == FIRSTPIN) {
if (match(sobj->model.class, obptr->model.class)) { if (match(sobj->model.class, obptr->model.class)) {
while (sobj->next->type > FIRSTPIN) while (sobj->next && (sobj->next->type > FIRSTPIN))
sobj = sobj->next; sobj = sobj->next;
/* Stop when reaching the current instance */ /* Stop when reaching the current instance */
if (sobj->type == obptr->type + 1) break; if (sobj->type == obptr->type + 1) break;