diff --git a/VERSION b/VERSION
index 37c8b13..c3e9958 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-1.5.213
+1.5.214
diff --git a/base/query.c b/base/query.c
index 1ab7979..a26a322 100644
--- a/base/query.c
+++ b/base/query.c
@@ -805,11 +805,13 @@ void DescribeInstance(char *name, int file)
       /* All black-box modules and placeholders by definition have all	*/
       /* disconnected pins, so don't report those.			*/
 
-      if ((!(tp->flags & CELL_PLACEHOLDER)) && (tp->class != CLASS_MODULE))
-      {
-	//if (disconnectednodes == 0) Fprintf(stderr, "\n");
+      if ((!(tp->flags & CELL_PLACEHOLDER)) && (tp->class != CLASS_MODULE)) {
+	// if (disconnectednodes == 0) Fprintf(stderr, "\n");
         disconnectednodes++;
-        Fprintf(stderr, "Cell %s(%d) disconnected node: %s\n", tp->name, tp->file, ob->name);
+	/* Don't report on ports marked "port_match_error", which is just confusing. */
+	if (strcmp(ob->name, "port_match_error")) {
+           Fprintf(stderr, "Cell %s(%d) disconnected node: %s\n", tp->name, tp->file, ob->name);
+	}
       }
     }
   }
diff --git a/base/verilog.c b/base/verilog.c
index b8d8b11..de66f95 100644
--- a/base/verilog.c
+++ b/base/verilog.c
@@ -2117,7 +2117,7 @@ nextinst:
 					sobj = sobj->next) {
 			      if (sobj->type == FIRSTPIN) {
 				 if (match(sobj->model.class, obptr->model.class)) {
-				    while (sobj->next->type > FIRSTPIN)
+				    while (sobj->next && (sobj->next->type > FIRSTPIN))
 				       sobj = sobj->next;
 				    /* Stop when reaching the current instance */
 				    if (sobj->type == obptr->type + 1) break;