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netgen
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Merge branch 'master' into netgen-1.5

This commit is contained in:
Tim Edwards 2021-07-12 03:00:10 -04:00
parent 9251ce2a48 064195ecc9
commit b6d896e73f
4 changed files with 18 additions and 8 deletions
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2
VERSION
View File

@ -1 +1 @@
1.5.194 1.5.195

7
base/netcmp.c
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@ -7560,7 +7560,8 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
} }
if (ob1 == NULL || ob1->type != PORT || ob1->node >= 0 if (ob1 == NULL || ob1->type != PORT || ob1->node >= 0
|| (ob1->node < 0 && tc1->class == CLASS_MODULE)) { || (ob1->node < 0 && tc1->class == CLASS_MODULE)
|| (ob1->node < 0 && ob1->model.port == -1)) {
/* Add a proxy pin to tc2 */ /* Add a proxy pin to tc2 */
obn = (struct objlist *)CALLOC(1, sizeof(struct objlist)); obn = (struct objlist *)CALLOC(1, sizeof(struct objlist));
@ -7577,8 +7578,7 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
obn->instance.name = NULL; obn->instance.name = NULL;
obn->node = -1; obn->node = -1;
#if 0 /* Note: Has this pin already been accounted for? */
/* Note: This pin has already been accounted for */
if (Debug == 0) { if (Debug == 0) {
if (strcmp(ob1->name, "(no pins)")) { if (strcmp(ob1->name, "(no pins)")) {
for (m = 0; m < left_col_end; m++) *(ostr + m) = ' '; for (m = 0; m < left_col_end; m++) *(ostr + m) = ' ';
@ -7594,7 +7594,6 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
Fprintf(stderr, "No netlist match for cell %s pin %s\n", Fprintf(stderr, "No netlist match for cell %s pin %s\n",
tc1->name, ob1->name); tc1->name, ob1->name);
} }
#endif
if (ob2 == tc2->cell) { if (ob2 == tc2->cell) {
obn->next = ob2; obn->next = ob2;

8
base/verilog.c
View File

@ -1577,6 +1577,14 @@ nextinst:
} }
new_port->net = wire_bundle; new_port->net = wire_bundle;
} }
else if (nexttok[0] == '~' || nexttok[0] == '!' || nexttok[0] == '-') {
/* All of these imply that the signal is logically manipulated */
/* in turn implying behavioral code. */
Printf("Module '%s' is not structural verilog, "
"making black-box.\n", model);
SetClass(CLASS_MODULE);
goto skip_endmodule;
}
else else
new_port->net = strsave(nexttok); new_port->net = strsave(nexttok);

9
tcltk/netgen.tcl.in
View File

@ -585,8 +585,7 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
netgen::log echo on netgen::log echo on
} }
} }
} elseif {$uresult > 0} { } else {
# Match pins
netgen::log echo off netgen::log echo off
if {$dolist == 1} { if {$dolist == 1} {
set result [equate -list pins "$fnum1 [lindex $endval 0]" \ set result [equate -list pins "$fnum1 [lindex $endval 0]" \
@ -599,7 +598,11 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
equate classes "$fnum1 [lindex $endval 0]" \ equate classes "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]" "$fnum2 [lindex $endval 1]"
} }
set pinsgood $result # If $uresult == -1 then these are black-box entries and
# $pinsgood should not be set to the resulting value.
if {$uresult > 0} {
set pinsgood $result
}
netgen::log echo on netgen::log echo on
} }
if {$uresult == 2} {lappend properr [lindex $endval 0]} if {$uresult == 2} {lappend properr [lindex $endval 0]}