diff --git a/VERSION b/VERSION
index b6834e4..464347a 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-1.5.194
+1.5.195
diff --git a/base/netcmp.c b/base/netcmp.c
index c04765b..e4f5d41 100644
--- a/base/netcmp.c
+++ b/base/netcmp.c
@@ -7560,7 +7560,8 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
       }
 
       if (ob1 == NULL || ob1->type != PORT || ob1->node >= 0
-		|| (ob1->node < 0 && tc1->class == CLASS_MODULE)) {
+		|| (ob1->node < 0 && tc1->class == CLASS_MODULE)
+		|| (ob1->node < 0 && ob1->model.port == -1)) {
 
 	 /* Add a proxy pin to tc2 */
          obn = (struct objlist *)CALLOC(1, sizeof(struct objlist));
@@ -7577,8 +7578,7 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
          obn->instance.name = NULL;
          obn->node = -1;
 
-#if 0
-	 /* Note:  This pin has already been accounted for */
+	 /* Note:  Has this pin already been accounted for? */
 	 if (Debug == 0) {
 	    if (strcmp(ob1->name, "(no pins)")) {
 	       for (m = 0; m < left_col_end; m++) *(ostr + m) = ' ';
@@ -7594,7 +7594,6 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
 	    Fprintf(stderr, "No netlist match for cell %s pin %s\n",
 				tc1->name, ob1->name);
 	 }
-#endif
 
 	 if (ob2 == tc2->cell) {
 	    obn->next = ob2;
diff --git a/base/verilog.c b/base/verilog.c
index 92dfbd1..f5ac6b0 100644
--- a/base/verilog.c
+++ b/base/verilog.c
@@ -1577,6 +1577,14 @@ nextinst:
 		     }
 		     new_port->net = wire_bundle;
 		  }
+		  else if (nexttok[0] == '~' || nexttok[0] == '!' || nexttok[0] == '-') {
+		     /* All of these imply that the signal is logically manipulated */
+		     /* in turn implying behavioral code.			    */
+		     Printf("Module '%s' is not structural verilog, "
+				    "making black-box.\n", model);
+		     SetClass(CLASS_MODULE);
+		     goto skip_endmodule;
+		  }
 		  else
 		     new_port->net = strsave(nexttok);
 
diff --git a/tcltk/netgen.tcl.in b/tcltk/netgen.tcl.in
index fc87cae..ba20352 100644
--- a/tcltk/netgen.tcl.in
+++ b/tcltk/netgen.tcl.in
@@ -585,8 +585,7 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
                    netgen::log echo on
 	       }
 	    }
-	 } elseif {$uresult > 0} {
-	    # Match pins
+	 } else {
             netgen::log echo off
 	    if {$dolist == 1} {
 		set result [equate -list pins "$fnum1 [lindex $endval 0]" \
@@ -599,7 +598,11 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
 		equate classes "$fnum1 [lindex $endval 0]" \
 			 "$fnum2 [lindex $endval 1]"
 	    }
-	    set pinsgood $result
+	    # If $uresult == -1 then these are black-box entries and
+	    # $pinsgood should not be set to the resulting value.
+	    if {$uresult > 0} {
+	        set pinsgood $result
+	    }
             netgen::log echo on
 	 }
 	 if {$uresult == 2} {lappend properr [lindex $endval 0]}