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netgen
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Merge branch 'master' into netgen-1.5

This commit is contained in:
Tim Edwards 2023-09-02 02:00:02 -04:00
parent bcbc736b51 cff954f36a
commit 9e9288f746
4 changed files with 18 additions and 15 deletions
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2
VERSION
View File

@ -1 +1 @@
1.5.256 1.5.257

16
base/flatten.c
View File

@ -1215,7 +1215,6 @@ int UniquePins(char *name, int filenum)
firstport = (struct objlist **)CALLOC(maxnode + 1, sizeof(struct objlist *)); firstport = (struct objlist **)CALLOC(maxnode + 1, sizeof(struct objlist *));
portcount = FIRSTPIN; portcount = FIRSTPIN;
lob = NULL;
for (ob = ThisCell->cell; ob != NULL; ob = ob->next) { for (ob = ThisCell->cell; ob != NULL; ob = ob->next) {
if (ob->type != PORT) break; if (ob->type != PORT) break;
if (ob->node > 0) { if (ob->node > 0) {
@ -1226,16 +1225,12 @@ int UniquePins(char *name, int filenum)
firstport[ob->node]->name, ThisCell->name, ThisCell->file); firstport[ob->node]->name, ThisCell->name, ThisCell->file);
/* Do not count this as a duplicate pin. */ /* Do not count this as a duplicate pin. */
nodecount[ob->node]--; nodecount[ob->node]--;
/* Move the pin adjacent to the one it is shorted to (if it /* Note: Previously there was code here to move the shorted port
* isn't already); this will make the work of MatchPins() easier. * next to the pin it is shorted to. This causes the cell def pins
* to become scrambled with respect to the pin order of its instances.
* Removed the code 9/1/2023. But---Not sure if any code depends
* on shorted pins being adjacent.
*/ */
if (firstport[ob->node]->next != ob) {
lob->next = ob->next;
ob->next = firstport[ob->node]->next;
firstport[ob->node]->next = ob;
ob = lob;
}
lob = ob;
continue; continue;
} }
else { else {
@ -1256,7 +1251,6 @@ int UniquePins(char *name, int filenum)
} }
} }
portcount++; portcount++;
lob = ob;
} }
if (needscleanup) if (needscleanup)

2
base/netcmp.c
View File

@ -7778,7 +7778,7 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
else if ((ob1->node != -1) && (ob2->node != -1)) { else if ((ob1->node != -1) && (ob2->node != -1)) {
/* Check for the case of ports on both sides being shorted /* Check for the case of ports on both sides being shorted
* together. That means that the nodes on both sides connect * together. That means that the nodes on both sides connect
* only to ports, that they connec to the same number of ports, * only to ports, that they connect to the same number of ports,
* and that each port pair has a matching name. * and that each port pair has a matching name.
*/ */
int onlyports = 1; int onlyports = 1;

13
base/verilog.c
View File

@ -1898,12 +1898,21 @@ skip_endmodule:
if (i != -1) if (i != -1)
snprintf(nodename, MAX_STR_LEN, "%s[%d]", noderoot, i); snprintf(nodename, MAX_STR_LEN, "%s[%d]", noderoot, i);
else else if (lhs != NULL)
strncpy(nodename, lhs->name, MAX_STR_LEN - 1); strncpy(nodename, lhs->name, MAX_STR_LEN - 1);
else {
Printf("Error: Improper node name \"%s\".\n", noderoot);
goto skip_endmodule;
}
if (j != -1) if (j != -1)
snprintf(assignname, MAX_STR_LEN, "%s[%d]", assignroot, j); snprintf(assignname, MAX_STR_LEN, "%s[%d]", assignroot, j);
else else if (rhs != NULL)
strncpy(assignname, rhs->name, MAX_STR_LEN - 1); strncpy(assignname, rhs->name, MAX_STR_LEN - 1);
else {
Printf("Error: Improper assignment name \"%s\".\n",
assignroot);
goto skip_endmodule;
}
join(nodename, assignname); join(nodename, assignname);