From c27d933adc2b790af9642169f602dfdd7a751da1 Mon Sep 17 00:00:00 2001 From: Tim Edwards Date: Fri, 1 Sep 2023 09:04:44 -0400 Subject: [PATCH 1/2] Modified some of the verilog read-in code to avoid a segmentation fault that would happen if the verilog had illegal syntax of a misspelled net name (although normally netgen is expected not to have to check the verilog for syntax, and there are probably many such cases of netgen failing to handle incorrect verilog and then crashing as a result). --- VERSION | 2 +- base/verilog.c | 13 +++++++++++-- 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/VERSION b/VERSION index 47d3fe3..b05db56 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -1.5.256 +1.5.257 diff --git a/base/verilog.c b/base/verilog.c index 9ba310c..f74d7ff 100644 --- a/base/verilog.c +++ b/base/verilog.c @@ -1898,12 +1898,21 @@ skip_endmodule: if (i != -1) snprintf(nodename, MAX_STR_LEN, "%s[%d]", noderoot, i); - else + else if (lhs != NULL) strncpy(nodename, lhs->name, MAX_STR_LEN - 1); + else { + Printf("Error: Improper node name \"%s\".\n", noderoot); + goto skip_endmodule; + } if (j != -1) snprintf(assignname, MAX_STR_LEN, "%s[%d]", assignroot, j); - else + else if (rhs != NULL) strncpy(assignname, rhs->name, MAX_STR_LEN - 1); + else { + Printf("Error: Improper assignment name \"%s\".\n", + assignroot); + goto skip_endmodule; + } join(nodename, assignname); From cff954f36a8ba8ca771c65dff15c1ac5a9113cd5 Mon Sep 17 00:00:00 2001 From: Tim Edwards Date: Fri, 1 Sep 2023 16:04:41 -0400 Subject: [PATCH 2/2] Removed a block of ill-considered code that moves pins together when they are shorted, because doing so is scrambling the pin order of cells with respect to the instance calls to the cell. Not sure if there is any code that relies on shorted pins being adjacent, though. --- base/flatten.c | 16 +++++----------- base/netcmp.c | 2 +- 2 files changed, 6 insertions(+), 12 deletions(-) diff --git a/base/flatten.c b/base/flatten.c index 1a48b2d..1f3b7dc 100644 --- a/base/flatten.c +++ b/base/flatten.c @@ -1215,7 +1215,6 @@ int UniquePins(char *name, int filenum) firstport = (struct objlist **)CALLOC(maxnode + 1, sizeof(struct objlist *)); portcount = FIRSTPIN; - lob = NULL; for (ob = ThisCell->cell; ob != NULL; ob = ob->next) { if (ob->type != PORT) break; if (ob->node > 0) { @@ -1226,16 +1225,12 @@ int UniquePins(char *name, int filenum) firstport[ob->node]->name, ThisCell->name, ThisCell->file); /* Do not count this as a duplicate pin. */ nodecount[ob->node]--; - /* Move the pin adjacent to the one it is shorted to (if it - * isn't already); this will make the work of MatchPins() easier. + /* Note: Previously there was code here to move the shorted port + * next to the pin it is shorted to. This causes the cell def pins + * to become scrambled with respect to the pin order of its instances. + * Removed the code 9/1/2023. But---Not sure if any code depends + * on shorted pins being adjacent. */ - if (firstport[ob->node]->next != ob) { - lob->next = ob->next; - ob->next = firstport[ob->node]->next; - firstport[ob->node]->next = ob; - ob = lob; - } - lob = ob; continue; } else { @@ -1256,7 +1251,6 @@ int UniquePins(char *name, int filenum) } } portcount++; - lob = ob; } if (needscleanup) diff --git a/base/netcmp.c b/base/netcmp.c index 0bfaec6..d05f8a8 100644 --- a/base/netcmp.c +++ b/base/netcmp.c @@ -7778,7 +7778,7 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist) else if ((ob1->node != -1) && (ob2->node != -1)) { /* Check for the case of ports on both sides being shorted * together. That means that the nodes on both sides connect - * only to ports, that they connec to the same number of ports, + * only to ports, that they connect to the same number of ports, * and that each port pair has a matching name. */ int onlyports = 1;