From 8a7bb7f2ca2b9283b750db61b4dd8084efabc9f5 Mon Sep 17 00:00:00 2001 From: Alessandro De Laurenzis Date: Sun, 17 Jan 2021 10:21:52 +0100 Subject: [PATCH] Fix missing prototype for ReadVerilogFile function Unbreak OpenBSD port for mips64 arch --- base/netgen.h | 9 +++++++++ base/spice.c | 9 --------- base/verilog.c | 5 ----- 3 files changed, 9 insertions(+), 14 deletions(-) diff --git a/base/netgen.h b/base/netgen.h index 90d28c1..9de7dfe 100644 --- a/base/netgen.h +++ b/base/netgen.h @@ -65,6 +65,15 @@ extern void AssignCircuits(char *name1, int file1, char *name2, int file2); /* flatten.c */ extern int PrematchLists(char *, int, char *, int); +/* verilog.c */ +struct cellstack { + char *cellname; + struct cellstack *next; +}; + +void ReadVerilogFile(char *fname, int filenum, struct cellstack **CellStackPtr, + int blackbox); + /* Define (enumerate) various device classes, largely based on SPICE */ /* model types, mixed with some ext/sim types. */ diff --git a/base/spice.c b/base/spice.c index 9f29b88..0209ded 100644 --- a/base/spice.c +++ b/base/spice.c @@ -473,15 +473,6 @@ void CleanupSubcell() { SetClass(CLASS_MODULE); } -/*------------------------------------------------------*/ -/* Structure for stacking nested subcircuit definitions */ -/*------------------------------------------------------*/ - -struct cellstack { - char *cellname; - struct cellstack *next; -}; - /*------------------------------------------------------*/ /* Push a subcircuit name onto the stack */ /*------------------------------------------------------*/ diff --git a/base/verilog.c b/base/verilog.c index b762d6f..8e2a802 100644 --- a/base/verilog.c +++ b/base/verilog.c @@ -632,11 +632,6 @@ void CleanupModule() { /* Structure for stacking nested module definitions */ /*------------------------------------------------------*/ -struct cellstack { - char *cellname; - struct cellstack *next; -}; - /* Forward declarations */ extern void IncludeVerilog(char *, int, struct cellstack **, int);