Corrected an error in the verilog parser that incorrectly handles

the syntax "assign a = b" when both a and b are vectors (but no
vector delimiters appear in the assignment).

base/verilog.c

@@ -1472,6 +1472,8 @@ skip_endmodule:
 			    rhs = LookupObject(assignname, CurrentCell);
 			    *aptr = '[';
 			}
+			else
+			    strcpy(assignroot, nexttok);
 		    }
 		    else {
 			j = -1;