From 89ef83c597d799be7777cdde7af6a6fb9f96bc29 Mon Sep 17 00:00:00 2001
From: Tim Edwards <tim@opencircuitdesign.com>
Date: Fri, 15 Apr 2022 14:13:11 -0400
Subject: [PATCH] Corrected an error in the verilog parser that incorrectly
 handles the syntax "assign a = b" when both a and b are vectors (but no
 vector delimiters appear in the assignment).

---
 base/verilog.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/base/verilog.c b/base/verilog.c
index 124a7d3..004c0cf 100644
--- a/base/verilog.c
+++ b/base/verilog.c
@@ -1472,6 +1472,8 @@ skip_endmodule:
 			    rhs = LookupObject(assignname, CurrentCell);
 			    *aptr = '[';
 			}
+			else
+			    strcpy(assignroot, nexttok);
 		    }
 		    else {
 			j = -1;