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netgen
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Found examples where the automated "pin matching" algorithm causes 

the top level circuits to be declared matching with no errors even
though the pins do not match.  "proxy pins" are fine for subcells
to detect cases where one subcell has an unused pin and the matching
subcell does not declare it, but that should not be allowed on the
top level, as it cannot be known whether the pin is unused or not.
This commit is contained in:
Tim Edwards 2020-08-08 13:19:26 -04:00
parent 82be18ec4b
commit 50b0e9cb65
3 changed files with 11 additions and 2 deletions
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2
VERSION
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@ -1 +1 @@
1.5.154 1.5.155

3
base/netcmp.c
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@ -7132,6 +7132,8 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
obn->instance.name = NULL; obn->instance.name = NULL;
obn->node = -1; obn->node = -1;
#if 0
/* Note: This pin has already been accounted for */
if (Debug == 0) { if (Debug == 0) {
if (strcmp(ob1->name, "(no pins)")) { if (strcmp(ob1->name, "(no pins)")) {
for (m = 0; m < left_col_end; m++) *(ostr + m) = ' '; for (m = 0; m < left_col_end; m++) *(ostr + m) = ' ';
@ -7147,6 +7149,7 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
Fprintf(stderr, "No netlist match for cell %s pin %s\n", Fprintf(stderr, "No netlist match for cell %s pin %s\n",
tc1->name, ob1->name); tc1->name, ob1->name);
} }
#endif
if (ob2 == tc2->cell) { if (ob2 == tc2->cell) {
obn->next = ob2; obn->next = ob2;

8
tcltk/netgen.tcl.in
View File

@ -501,6 +501,7 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
return return
} }
set properr {} set properr {}
set pinsgood 0
while {$endval != {}} { while {$endval != {}} {
if {$dolist == 1} { if {$dolist == 1} {
netgen::run -list converge netgen::run -list converge
@ -546,6 +547,7 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
equate classes "$fnum1 [lindex $endval 0]" \ equate classes "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]" "$fnum2 [lindex $endval 1]"
} }
set pinsgood $result
netgen::log echo on netgen::log echo on
} }
if {$uresult == 2} {lappend properr [lindex $endval 0]} if {$uresult == 2} {lappend properr [lindex $endval 0]}
@ -569,7 +571,11 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
netgen::log echo off netgen::log echo off
puts stdout "Result: " nonewline puts stdout "Result: " nonewline
netgen::log echo on netgen::log echo on
verify only if {$pinsgood == 0} {
netgen::log put "The top level cell failed pin matching.\n"
} else {
verify only
}
if {$properr != {}} { if {$properr != {}} {
netgen::log put "The following cells had property errors: $properr\n" netgen::log put "The following cells had property errors: $properr\n"
} }