From 50b0e9cb6572cfa2f96d49556d13e4c445986e0f Mon Sep 17 00:00:00 2001
From: Tim Edwards <tim@opencircuitdesign.com>
Date: Sat, 8 Aug 2020 13:19:26 -0400
Subject: [PATCH] Found examples where the automated "pin matching" algorithm
 causes the top level circuits to be declared matching with no errors even
 though the pins do not match.  "proxy pins" are fine for subcells to detect
 cases where one subcell has an unused pin and the matching subcell does not
 declare it, but that should not be allowed on the top level, as it cannot be
 known whether the pin is unused or not.

---
 VERSION             | 2 +-
 base/netcmp.c       | 3 +++
 tcltk/netgen.tcl.in | 8 +++++++-
 3 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/VERSION b/VERSION
index 1fd08a2..df85035 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-1.5.154
+1.5.155
diff --git a/base/netcmp.c b/base/netcmp.c
index 2d83357..8db52c4 100644
--- a/base/netcmp.c
+++ b/base/netcmp.c
@@ -7132,6 +7132,8 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
          obn->instance.name = NULL;
          obn->node = -1;
 
+#if 0
+	 /* Note:  This pin has already been accounted for */
 	 if (Debug == 0) {
 	    if (strcmp(ob1->name, "(no pins)")) {
 	       for (m = 0; m < left_col_end; m++) *(ostr + m) = ' ';
@@ -7147,6 +7149,7 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
 	    Fprintf(stderr, "No netlist match for cell %s pin %s\n",
 				tc1->name, ob1->name);
 	 }
+#endif
 
 	 if (ob2 == tc2->cell) {
 	    obn->next = ob2;
diff --git a/tcltk/netgen.tcl.in b/tcltk/netgen.tcl.in
index 561f469..431bcf1 100644
--- a/tcltk/netgen.tcl.in
+++ b/tcltk/netgen.tcl.in
@@ -501,6 +501,7 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
       return
    }
    set properr {}
+   set pinsgood 0
    while {$endval != {}} {
       if {$dolist == 1} {
          netgen::run -list converge
@@ -546,6 +547,7 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
 		equate classes "$fnum1 [lindex $endval 0]" \
 			 "$fnum2 [lindex $endval 1]"
 	    }
+	    set pinsgood $result
             netgen::log echo on
 	 }
 	 if {$uresult == 2} {lappend properr [lindex $endval 0]}
@@ -569,7 +571,11 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
    netgen::log echo off
    puts stdout "Result: " nonewline
    netgen::log echo on
-   verify only
+   if {$pinsgood == 0} {
+      netgen::log put "The top level cell failed pin matching.\n"
+   } else {
+      verify only
+   }
    if {$properr != {}} {
       netgen::log put "The following cells had property errors: $properr\n"
    }