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Added code to handle the problem in which a verilog netlist is read before its component cells, and the component cells are read in as SPICE netlists. Then the original verilog cell and its instances need to have pins reordered to match the subcircuit definition in the SPICE netlist. Otherwise, when verilog and SPICE netlists are mixed, the order in which the files are read is critical, and failures due to reading out-of-order are very obscure and nearly impossible to debug.
2024-02-04 03:21:09 +01:00
1.5.267