Updated Configuring a Core (markdown)

Configuring-a-Core.md

@@ -1,4 +1,15 @@
-Downlink:
+# Downlink:
+## Modes:
+* __Single-Shot__: When a condition is met, grab the whole thing.
+* __Incremental__: Only pull values when trigger condition is received.
+* __Immediate__: Pull values immediately, regardless of if the trigger condition is met or not.
 
 
-Upload:
+
+# Upload:
+
+# Roadmap / Ongoing Questions:
+* _Configurable Trigger Location:_ Instead of always centering the downlink core's waveform around where the trigger condition is met, you might want to grab everything before or after the trigger. Or even things that are some number of clock cycles ahead or behind of the trigger. Being able to specify this 'holdoff' or 'position' in the downlink core configuration would be nice. Especially if it's something as simple as `beginning`, `middle`, `end`, or just a number of clock cycles.
+* _Configurable Clock Edge:_ Right now when we add a waveform to a VCD file, we assume that all the values change on the rising edge of the ILA clock. And that's true - we sample them on the rising edge of the input clock. I don't know if we'd want to add an option for clocking in things on the falling edge - I think that's going to make timing hard and students confused.
+* _Reconfigurable uplink cores:_ Instead of loading a BRAM with some fixed content and calling it a day, we should be able to load new data into that memory, and then dump it to the system when needed.
+* _Clock Domain Crossing:_ You should be able to put cores in different clock domains - although I'm struggling to figure out where exactly this would be useful. Xilinx's ILA will let you have multiple cores and it doesn't care much which clock domain those are under, so some more investigation will be needed there.