62 lines
1.5 KiB
Python
62 lines
1.5 KiB
Python
from amaranth.sim import Simulator
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from manta.uart import UARTReceiver
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from manta.utils import *
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from random import sample
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uart_rx = UARTReceiver(clocks_per_baud=10)
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def verify_receive(data):
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# 8N1 serial, LSB sent first
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data_bits = "0" + f"{data:08b}"[::-1] + "1"
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data_bits = [int(bit) for bit in data_bits]
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valid_asserted_before = False
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for i in range(10 * uart_rx._clocks_per_baud):
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bit_index = i // uart_rx._clocks_per_baud
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# Every cycle, run checks on uart_rx:
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if (yield uart_rx.valid_o):
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if (yield uart_rx.data_o) != data:
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a = yield uart_rx.data_o
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print(data_bits)
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raise ValueError(
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f"Incorrect byte presented - gave {hex(a)} instead of {hex(data)}!"
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)
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if bit_index != 9:
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print(bit_index)
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raise ValueError("Byte presented before it is complete!")
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if not valid_asserted_before:
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valid_asserted_before = True
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else:
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raise ValueError("Valid asserted more than once!")
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yield uart_rx.rx.eq(data_bits[bit_index])
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yield
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if not valid_asserted_before:
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raise ValueError("Failed to assert valid!")
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@simulate(uart_rx)
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def test_all_possible_bytes():
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yield uart_rx.rx.eq(1)
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yield
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for i in range(0xFF):
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yield from verify_receive(i)
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@simulate(uart_rx)
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def test_bytes_random_sample():
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yield uart_rx.rx.eq(1)
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yield
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for i in jumble(range(0xFF)):
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yield from verify_receive(i)
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