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manta
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manta/src/manta
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Fischer Moseley f5caca613a simplify uart/ether APIs, improve lazy loading 2023-04-28 14:57:36 -04:00
..
block_mem_core simplify uart/ether APIs, improve lazy loading 2023-04-28 14:57:36 -04:00
ether_iface simplify uart/ether APIs, improve lazy loading 2023-04-28 14:57:36 -04:00
io_core simplify uart/ether APIs, improve lazy loading 2023-04-28 14:57:36 -04:00
la_core simplify uart/ether APIs, improve lazy loading 2023-04-28 14:57:36 -04:00
lut_mem_core simplify uart/ether APIs, improve lazy loading 2023-04-28 14:57:36 -04:00
uart_iface simplify uart/ether APIs, improve lazy loading 2023-04-28 14:57:36 -04:00
__init__.py simplify uart/ether APIs, improve lazy loading 2023-04-28 14:57:36 -04:00
__main__.py add linting to makefile, update bus testbenches 2023-03-14 16:24:56 -04:00
hdl_utils.py enforce consistent naming of lut_mem module 2023-04-28 14:57:36 -04:00
manta_def_tmpl.v add working ethernet verilog autogeneration woot woot :) 2023-04-28 14:57:36 -04:00