84 lines
1.3 KiB
Systemverilog
84 lines
1.3 KiB
Systemverilog
`default_nettype none
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`timescale 1ns / 1ps
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module uart_tb();
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logic clk;
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logic rst;
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logic [7:0] tx_data;
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logic tx_start;
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// transmitters
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logic tx_done_manta;
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logic txd_manta;
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uart_tx #(.CLOCKS_PER_BAUD(10)) tx_manta (
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.clk(clk),
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.data_i(tx_data),
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.start_i(tx_start),
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.done_o(tx_done_manta),
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.tx(txd_manta));
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logic tx_busy_zipcpu;
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logic tx_done_zipcpu;
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logic txd_zipcpu;
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assign tx_done_zipcpu = ~tx_busy_zipcpu;
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tx_uart #(.CLOCKS_PER_BAUD(10)) tx_zipcpu (
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.i_clk(clk),
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.i_wr(tx_start),
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.i_data(tx_data),
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.o_uart_tx(txd_zipcpu),
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.o_busy(tx_busy_zipcpu));
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// receivers
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logic [7:0] rx_data_manta;
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logic rx_valid_manta;
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uart_rx #(.CLOCKS_PER_BAUD(10)) rx_manta (
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.clk(clk),
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.rx(txd_manta),
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.data_o(rx_data_manta),
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.valid_o(rx_valid_manta));
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logic [7:0] rx_data_zipcpu;
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logic rx_valid_zipcpu;
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rx_uart #(.CLOCKS_PER_BAUD(10)) rx_zipcpu (
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.i_clk(clk),
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.i_uart_rx(txd_zipcpu),
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.o_wr(rx_valid_zipcpu),
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.o_data(rx_data_zipcpu));
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always begin
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#5;
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clk = !clk;
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end
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initial begin
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$dumpfile("uart.vcd");
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$dumpvars(0, uart_tb);
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clk = 0;
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tx_data = 'hFF;
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tx_start = 0;
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#10;
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rst = 0;
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#10;
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tx_start = 1;
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#10;
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tx_start = 0;
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#10000;
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// send another byte!
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tx_data = 'b0100_1101;
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tx_start = 1;
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#3000;
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tx_start = 0;
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#10000;
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$finish();
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end
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endmodule
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`default_nettype wire
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