36 lines
620 B
Systemverilog
36 lines
620 B
Systemverilog
`default_nettype none
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`timescale 1ns / 1ps
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`include "manta.v"
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module top_level (
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input wire clk,
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input wire rs232_rx_ttl,
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output logic rs232_tx_ttl
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);
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logic [9:0] counter;
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always @(posedge clk) counter <= counter + 1;
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assign probe0 = counter[0];
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assign probe1 = counter[2:1];
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assign probe2 = counter[5:3];
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assign probe4 = counter[9:6];
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manta manta_inst (
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.clk(clk),
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.rst(0),
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.rx(rs232_rx_ttl),
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.tx(rs232_tx_ttl),
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.probe0(probe0),
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.probe1(probe1),
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.probe2(probe2),
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.probe3(probe3));
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endmodule
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`default_nettype wire
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