manta/examples/verilog/icestick/uart_logic_analyzer/manta.yaml

21 lines
290 B
YAML

---
cores:
my_logic_analyzer:
type: logic_analyzer
sample_depth: 2048
trigger_mode: single_shot
probes:
probe0: 1
probe1: 2
probe2: 3
probe3: 4
triggers:
- probe2 EQ 3
uart:
port: "/dev/ttyUSB3"
baudrate: 115200
clock_freq: 12e6