70 lines
2.0 KiB
Makefile
70 lines
2.0 KiB
Makefile
build:
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python3 -m build
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pypi_upload: build
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python3 -m twine upload --repository testpypi dist/*
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lint:
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python3 -m black src/manta/__init__.py
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python3 -m black src/manta/__main__.py
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sim: io_core_tb logic_analyzer_tb bit_fifo_tb bridge_rx_tb bridge_tx_tb fifo_tb lut_ram_tb uart_tb uart_tx_tb
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io_core_tb:
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iverilog -g2012 -o sim.out test/io_core_tb.sv src/manta/io_core.v
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vvp sim.out
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rm sim.out
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logic_analyzer_tb:
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iverilog -g2012 -o sim.out test/logic_analyzer_tb.sv src/manta/logic_analyzer.v src/manta/la_fsm.v src/manta/trigger_block.v src/manta/trigger.v src/manta/sample_mem.v src/manta/xilinx_true_dual_port_read_first_2_clock_ram.v
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vvp sim.out
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rm sim.out
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bit_fifo_tb:
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iverilog -g2012 -o sim.out test/bit_fifo_tb.sv src/manta/bit_fifo.v
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vvp sim.out
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rm sim.out
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bridge_rx_tb:
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iverilog -g2012 -o sim.out test/bridge_rx_tb.sv src/manta/bridge_rx.v
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vvp sim.out
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rm sim.out
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bridge_tx_tb:
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iverilog -g2012 -o sim.out test/bridge_tx_tb.sv src/manta/bridge_tx.v src/manta/uart_tx.v
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vvp sim.out
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rm sim.out
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fifo_tb:
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iverilog -g2012 -o sim.out test/fifo_tb.sv src/manta/fifo.v src/manta/xilinx_true_dual_port_read_first_2_clock_ram.v
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vvp sim.out >> /dev/null # this one is noisy right now
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rm sim.out
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lut_ram_tb:
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iverilog -g2012 -o sim.out test/lut_ram_tb.sv src/manta/lut_ram.v
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vvp sim.out
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rm sim.out
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uart_tb:
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iverilog -g2012 -o sim.out test/uart_tb.sv src/manta/tx_uart.v src/manta/uart_rx.v
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vvp sim.out
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rm sim.out
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uart_tx_tb:
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iverilog -g2012 -o sim.out test/uart_tx_tb.sv src/manta/tx_uart.v src/manta/uart_tx.v src/manta/rx_uart.v
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vvp sim.out
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rm sim.out
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clean:
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rm -f *.out *.vcd
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rm -rf dist/
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rm -rf src/mantaray.egg-info
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serve_docs:
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mkdocs serve
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total_loc:
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find . -type f \( -iname \*.sv -o -iname \*.v -o -iname \*.py -o -iname \*.yaml -o -iname \*.yml -o -iname \*.md \) | sed 's/.*/"&"/' | xargs wc -l
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real_loc:
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find src test -type f \( -iname \*.sv -o -iname \*.v -o -iname \*.py -o -iname \*.yaml -o -iname \*.md \) | sed 's/.*/"&"/' | xargs wc -l
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