76 lines
1.3 KiB
Systemverilog
76 lines
1.3 KiB
Systemverilog
`default_nettype none
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`timescale 1ns/1ps
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module mac_tb();
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logic clk;
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always begin
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#5;
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clk = !clk;
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end
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logic crsdv;
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logic [1:0] rxd;
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logic txen;
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logic [1:0] txd;
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logic [15:0] mtx_data;
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logic [15:0] mtx_ethertype;
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logic mtx_start;
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logic [15:0] mrx_data;
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logic [15:0] mrx_ethertype;
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logic mrx_valid;
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mac_tx mtx (
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.clk(clk),
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.data(mtx_data),
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.ethertype(mtx_ethertype),
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.start(mtx_start),
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.txen(txen),
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.txd(txd));
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assign rxd = txd;
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assign crsdv = txen;
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mac_rx mrx (
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.clk(clk),
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.crsdv(crsdv),
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.rxd(rxd),
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.data(mrx_data),
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.ethertype(mrx_ethertype),
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.valid(mrx_valid));
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initial begin
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$dumpfile("mac_tb.vcd");
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$dumpvars(0, mac_tb);
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clk = 0;
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mtx_ethertype = 0;
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mtx_data = 0;
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mtx_start = 0;
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#10;
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for (int i=0; i<128; i=i+1) begin
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mtx_data = i;
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mtx_ethertype = i;
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mtx_start = 0;
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#10;
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mtx_start = 1;
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#10;
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mtx_start = 0;
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while(!mrx_valid) #10;
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#1000;
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assert(mrx_data == i) else $error("data mismatch!");
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end
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$finish();
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end
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endmodule
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`default_nettype wire |