56 lines
1.5 KiB
Systemverilog
56 lines
1.5 KiB
Systemverilog
`timescale 1ns / 1ps
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module top_level(
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input wire clk,
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input wire sd_cd,
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input wire btnc,
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output logic [15:0] led,
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inout [3:0] sd_dat,
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output logic sd_reset,
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output logic sd_sck,
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output logic sd_cmd
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);
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assign sd_dat[2:1] = 2'b11;
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assign sd_reset = 0;
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// generate 25 mhz clock for sd_controller
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logic clk_25mhz;
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sd_clk_gen clk_gen(
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.clk_100mhz(clk),
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.clk_25mhz(clk_25mhz));
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// sd_controller inputs
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logic rd; // read enable
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logic wr; // write enable
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logic [7:0] din; // data to sd card
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logic [31:0] addr; // starting address for read/write operation
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// sd_controller outputs
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logic ready; // high when ready for new read/write operation
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logic [7:0] dout; // data from sd card
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logic byte_available; // high when byte available for read
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logic ready_for_next_byte; // high when ready for new byte to be written
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// handles reading from the SD card
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sd_controller sd(
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.reset(btnc),
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.clk(clk_25mhz),
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.cs(sd_dat[3]),
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.mosi(sd_cmd),
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.miso(sd_dat[0]),
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.sclk(sd_sck),
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.ready(ready),
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.address(addr),
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.rd(rd),
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.dout(dout),
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.byte_available(byte_available),
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.wr(wr),
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.din(din),
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.ready_for_next_byte(ready_for_next_byte));
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// your Verilog here :)
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endmodule |