199 lines
6.6 KiB
Verilog
199 lines
6.6 KiB
Verilog
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// file: sd_clk_gen.v
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//
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// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//----------------------------------------------------------------------------
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// User entered comments
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//----------------------------------------------------------------------------
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// None
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//
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//----------------------------------------------------------------------------
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// Output Output Phase Duty Cycle Pk-to-Pk Phase
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// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
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//----------------------------------------------------------------------------
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// clk_25mhz__25.00000______0.000______50.0______181.828____104.359
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//
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//----------------------------------------------------------------------------
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// Input Clock Freq (MHz) Input Jitter (UI)
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//----------------------------------------------------------------------------
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// __primary_________100.000____________0.010
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`timescale 1ps/1ps
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module sd_clk_gen
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(// Clock in ports
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// Clock out ports
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output clk_25mhz,
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input clk_100mhz
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);
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// Input buffering
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//------------------------------------
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wire clk_100mhz_sd_clk_gen;
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wire clk_in2_sd_clk_gen;
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IBUF clkin1_ibufg
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(.O (clk_100mhz_sd_clk_gen),
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.I (clk_100mhz));
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// Clocking PRIMITIVE
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//------------------------------------
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// Instantiation of the MMCM PRIMITIVE
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// * Unused inputs are tied off
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// * Unused outputs are labeled unused
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wire clk_25mhz_sd_clk_gen;
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wire clk_out2_sd_clk_gen;
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wire clk_out3_sd_clk_gen;
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wire clk_out4_sd_clk_gen;
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wire clk_out5_sd_clk_gen;
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wire clk_out6_sd_clk_gen;
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wire clk_out7_sd_clk_gen;
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wire [15:0] do_unused;
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wire drdy_unused;
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wire psdone_unused;
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wire locked_int;
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wire clkfbout_sd_clk_gen;
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wire clkfbout_buf_sd_clk_gen;
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wire clkfboutb_unused;
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wire clkout0b_unused;
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wire clkout1_unused;
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wire clkout1b_unused;
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wire clkout2_unused;
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wire clkout2b_unused;
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wire clkout3_unused;
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wire clkout3b_unused;
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wire clkout4_unused;
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wire clkout5_unused;
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wire clkout6_unused;
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wire clkfbstopped_unused;
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wire clkinstopped_unused;
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MMCME2_ADV
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#(.BANDWIDTH ("OPTIMIZED"),
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.CLKOUT4_CASCADE ("FALSE"),
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.COMPENSATION ("ZHOLD"),
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.STARTUP_WAIT ("FALSE"),
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.DIVCLK_DIVIDE (1),
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.CLKFBOUT_MULT_F (9.125),
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.CLKFBOUT_PHASE (0.000),
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.CLKFBOUT_USE_FINE_PS ("FALSE"),
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.CLKOUT0_DIVIDE_F (36.500),
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.CLKOUT0_PHASE (0.000),
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.CLKOUT0_DUTY_CYCLE (0.500),
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.CLKOUT0_USE_FINE_PS ("FALSE"),
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.CLKIN1_PERIOD (10.000))
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mmcm_adv_inst
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// Output clocks
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(
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.CLKFBOUT (clkfbout_sd_clk_gen),
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.CLKFBOUTB (clkfboutb_unused),
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.CLKOUT0 (clk_25mhz_sd_clk_gen),
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.CLKOUT0B (clkout0b_unused),
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.CLKOUT1 (clkout1_unused),
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.CLKOUT1B (clkout1b_unused),
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.CLKOUT2 (clkout2_unused),
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.CLKOUT2B (clkout2b_unused),
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.CLKOUT3 (clkout3_unused),
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.CLKOUT3B (clkout3b_unused),
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.CLKOUT4 (clkout4_unused),
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.CLKOUT5 (clkout5_unused),
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.CLKOUT6 (clkout6_unused),
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// Input clock control
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.CLKFBIN (clkfbout_buf_sd_clk_gen),
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.CLKIN1 (clk_100mhz_sd_clk_gen),
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.CLKIN2 (1'b0),
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// Tied to always select the primary input clock
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.CLKINSEL (1'b1),
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// Ports for dynamic reconfiguration
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.DADDR (7'h0),
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.DCLK (1'b0),
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.DEN (1'b0),
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.DI (16'h0),
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.DO (do_unused),
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.DRDY (drdy_unused),
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.DWE (1'b0),
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// Ports for dynamic phase shift
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.PSCLK (1'b0),
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.PSEN (1'b0),
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.PSINCDEC (1'b0),
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.PSDONE (psdone_unused),
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// Other control and status signals
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.LOCKED (locked_int),
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.CLKINSTOPPED (clkinstopped_unused),
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.CLKFBSTOPPED (clkfbstopped_unused),
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.PWRDWN (1'b0),
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.RST (1'b0));
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// Clock Monitor clock assigning
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//--------------------------------------
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// Output buffering
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//-----------------------------------
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BUFG clkf_buf
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(.O (clkfbout_buf_sd_clk_gen),
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.I (clkfbout_sd_clk_gen));
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BUFG clkout1_buf
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(.O (clk_25mhz),
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.I (clk_25mhz_sd_clk_gen));
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endmodule
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