101 lines
2.8 KiB
Python
101 lines
2.8 KiB
Python
from amaranth.sim import Simulator
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from manta.logic_analyzer import LogicAnalyzerCore
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from manta.logic_analyzer.trigger_block import Operations
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from manta.utils import *
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from random import sample
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config = {
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"type": "logic_analyzer",
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"sample_depth": 1024,
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"trigger_location": 512,
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"probes": {"larry": 1, "curly": 3, "moe": 9},
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"triggers": ["moe RISING"],
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}
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la = LogicAnalyzerCore(config, base_addr=0, interface=None)
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async def print_data_at_addr(ctx, addr):
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# place read transaction on the bus
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ctx.set(la.bus_i.addr, addr)
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ctx.set(la.bus_i.data, 0)
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ctx.set(la.bus_i.rw, 0)
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ctx.set(la.bus_i.valid, True)
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await ctx.tick()
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ctx.set(la.bus_i.addr, 0)
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ctx.set(la.bus_i.valid, 0)
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# wait for output to be valid
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while not ctx.get(la.bus_o.valid):
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await ctx.tick()
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print(f"addr: {hex(addr)} data: {hex(ctx.get(la.bus_o.data))}")
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async def set_fsm_register(ctx, name, data):
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addr = la._fsm.registers._memory_map[name]["addrs"][0]
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strobe_addr = la._fsm.registers._base_addr
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await write_register(la, ctx, strobe_addr, 0)
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await write_register(la, ctx, addr, data)
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await write_register(la, ctx, strobe_addr, 1)
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await write_register(la, ctx, strobe_addr, 0)
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async def set_trig_blk_register(ctx, name, data):
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addr = la._trig_blk.registers._memory_map[name]["addrs"][0]
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strobe_addr = la._trig_blk.registers._base_addr
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await write_register(la, ctx, strobe_addr, 0)
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await write_register(la, ctx, addr, data)
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await write_register(la, ctx, strobe_addr, 1)
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await write_register(la, ctx, strobe_addr, 0)
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async def set_probe(ctx, name, value):
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probe = None
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for p in la._probes:
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if p.name == name:
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probe = p
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ctx.set(probe, value)
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@simulate(la)
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async def test_single_shot_capture(ctx):
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# request FSM to stop
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await set_fsm_register(ctx, "request_stop", 1)
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await set_fsm_register(ctx, "request_stop", 0)
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# setting triggers
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await set_trig_blk_register(ctx, "curly_op", Operations.EQ)
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await set_trig_blk_register(ctx, "curly_arg", 4)
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# setting trigger mode
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await set_fsm_register(ctx, "trigger_mode", 0)
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# setting trigger location
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await set_fsm_register(ctx, "trigger_location", 511)
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# starting capture
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await set_fsm_register(ctx, "request_start", 1)
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await set_fsm_register(ctx, "request_start", 0)
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# wait a few hundred clock cycles, see what happens
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await ctx.tick().repeat(700)
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# provide the trigger condition
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await set_probe(ctx, "curly", 4)
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await ctx.tick().repeat(700)
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# dump sample memory contents
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await write_register(la, ctx, 0, 0)
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await write_register(la, ctx, 0, 1)
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await write_register(la, ctx, 0, 0)
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for addr in range(la.max_addr):
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await print_data_at_addr(ctx, addr)
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