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manta/examples/verilog/icestick/io_core_uart
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Fischer Moseley 60066ccdca add examples for the Nexys4DDR, bump version to 1.0.0 2024-03-06 23:07:20 -08:00
..
.gitignore add logic analyzer icestick example 2024-03-06 22:05:24 -08:00
blinky.py add examples for the Nexys4DDR, bump version to 1.0.0 2024-03-06 23:07:20 -08:00
build.sh add logic analyzer icestick example 2024-03-06 22:05:24 -08:00
manta.yaml add logic analyzer icestick example 2024-03-06 22:05:24 -08:00
top_level.pcf add logic analyzer icestick example 2024-03-06 22:05:24 -08:00
top_level.sv add logic analyzer icestick example 2024-03-06 22:05:24 -08:00