100 lines
1.9 KiB
Systemverilog
100 lines
1.9 KiB
Systemverilog
`default_nettype none
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`define CP 10
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`define HCP 5
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task automatic transmit_byte (
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input [7:0] data,
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input integer CLOCKS_PER_BAUD
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);
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// send a byte from uart_tx, and check that it transmits properly
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integer data_bit = 0;
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for(int i=0; i < (10*CLOCKS_PER_BAUD)-1; i++) begin
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// check that data bit is correct on every baud period
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data_bit = i / CLOCKS_PER_BAUD;
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if (data_bit == 0) begin
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assert(uart_tx_tb.utx_tb_tx == 0) else $fatal(0, "wrong start bit!");
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end
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else if ((data_bit > 0) && (data_bit < 9)) begin
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assert(uart_tx_tb.utx_tb_tx == data[data_bit-1]) else $fatal(0, "wrong data bit!");
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end
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else begin
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assert(uart_tx_tb.utx_tb_tx == 1) else $fatal(0, "wrong stop bit!");
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end
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// check that done is not asserted during transmisison
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assert(!uart_tx_tb.utx_tb_done) else $fatal(0, "wrong done!");
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#`CP;
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end
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// assert that done is asserted at end of transmission
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assert(uart_tx_tb.utx_tb_done) else $fatal(0, "wrong done!");
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endtask
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module uart_tx_tb();
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logic clk;
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integer test_num;
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logic [7:0] tb_utx_data;
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logic tb_utx_start;
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logic utx_tb_done;
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logic utx_tb_tx;
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uart_tx #(.CLOCKS_PER_BAUD(10)) utx (
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.clk(clk),
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.data_i(tb_utx_data),
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.start_i(tb_utx_start),
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.done_o(utx_tb_done),
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.tx(utx_tb_tx));
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always begin
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#`HCP
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clk = !clk;
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end
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initial begin
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$dumpfile("uart_tx_tb.vcd");
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$dumpvars(0, uart_tx_tb);
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clk = 0;
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test_num = 0;
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tb_utx_data = 0;
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tb_utx_start = 0;
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#`HCP;
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// test all possible bytes
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test_num = test_num + 1;
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for(int i=0; i < 256; i++) begin
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tb_utx_start = 1;
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tb_utx_data = i;
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#`CP;
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tb_utx_start = 0;
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tb_utx_data = 0;
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transmit_byte(i, 10);
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#(100*`CP);
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end
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// test all possible bytes (no delay between them)
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test_num = test_num + 1;
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for(int i=0; i < 256; i++) begin
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tb_utx_start = 1;
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tb_utx_data = i;
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#`CP;
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tb_utx_data = 0;
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transmit_byte(i, 10);
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end
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$finish();
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end
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endmodule
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`default_nettype wire
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