95 lines
2.1 KiB
Systemverilog
95 lines
2.1 KiB
Systemverilog
`default_nettype none
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`define CP 10
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`define HCP 5
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task automatic test_receive (
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input [7:0] data,
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input integer CLOCKS_PER_BAUD
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);
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// send a byte to uart_rx, and check that it receives properly
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integer data_bit = 0;
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logic valid_has_been_asserted = 0;
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for(int i=0; i < (10*CLOCKS_PER_BAUD); i++) begin
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// clock out data bits on each baud period
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data_bit = i / CLOCKS_PER_BAUD;
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if (data_bit == 0) uart_rx_tb.tb_urx_rx = 0;
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else if ((data_bit > 0) && (data_bit < 9)) uart_rx_tb.tb_urx_rx = data[data_bit-1];
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else uart_rx_tb.tb_urx_rx = 1;
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// every cycle, run checks on uart_rx:
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// make sure valid isn't asserted before end of byte
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if (data_bit < 9) begin
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assert(uart_rx_tb.urx_tb_valid == 0) else $fatal(0, "valid asserted before end of byte!");
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end
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// make sure valid is only asserted once
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if (valid_has_been_asserted) begin
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assert(uart_rx_tb.urx_tb_valid == 0) else $fatal(0, "valid asserted more than once!");
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end
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// make sure byte is presented once last bit has been clocked out
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if (uart_rx_tb.urx_tb_valid) begin
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assert(data_bit == 9) else $fatal(0, "byte presented before it is complete");
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assert(uart_rx_tb.urx_tb_data == data) else $fatal(0, "wrong data!");
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valid_has_been_asserted = 1;
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end
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#`CP;
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end
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// make sure valid was asserted at some point
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assert (valid_has_been_asserted) else $fatal(0, "valid not asserted!");
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endtask
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module uart_rx_tb();
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logic clk;
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integer test_num;
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logic tb_urx_rx;
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logic [7:0] urx_tb_data;
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logic urx_tb_valid;
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uart_rx #(.CLOCKS_PER_BAUD(10)) urx (
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.clk(clk),
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.rx(tb_urx_rx),
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.data_o(urx_tb_data),
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.valid_o(urx_tb_valid));
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always begin
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#`HCP
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clk = !clk;
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end
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initial begin
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$dumpfile("uart_rx_tb.vcd");
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$dumpvars(0, uart_rx_tb);
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clk = 0;
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test_num = 0;
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tb_urx_rx = 1;
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#`HCP;
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// test all possible bytes
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test_num = test_num + 1;
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for(int i=0; i < 256; i++) begin
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test_receive(i, 10);
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#(100*`CP);
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end
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// test all possible bytes (no delay between them)
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test_num = test_num + 1;
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for(int i=0; i < 256; i++) begin
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test_receive(i, 10);
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end
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$finish();
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end
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endmodule
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`default_nettype wire
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