86 lines
1.6 KiB
Systemverilog
86 lines
1.6 KiB
Systemverilog
`default_nettype none
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`timescale 1ns/1ps
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`define FPGA_MAC 48'h69_69_5A_06_54_91
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`define HOST_MAC 48'h00_E0_4C_68_1E_0C
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`define ETHERTYPE 16'h88_B5
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module mac_tb();
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logic clk;
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always begin
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#5;
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clk = !clk;
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end
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logic crsdv;
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logic [1:0] rxd;
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logic txen;
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logic [1:0] txd;
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// this testbench makes sure that our rx pipeline is good,
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// so we'll have mtx simulate the host machine and blast
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// 5 bytes (plus padding) onto our fake RMII
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logic [39:0] mtx_payload;
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logic mtx_start;
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logic [39:0] mrx_payload;
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logic mrx_valid;
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mac_tx #(
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.SRC_MAC(`HOST_MAC),
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.DST_MAC(`FPGA_MAC),
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.ETHERTYPE(`ETHERTYPE),
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.PAYLOAD_LENGTH_BYTES(5)
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) mtx (
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.clk(clk),
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.payload(mtx_payload),
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.start(mtx_start),
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.txen(txen),
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.txd(txd));
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assign rxd = txd;
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assign crsdv = txen;
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mac_rx #(
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.FPGA_MAC(`FPGA_MAC),
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.ETHERTYPE(`ETHERTYPE)
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) mrx (
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.clk(clk),
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.crsdv(crsdv),
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.rxd(rxd),
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.payload(mrx_payload),
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.valid(mrx_valid));
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initial begin
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$dumpfile("mac_tb.vcd");
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$dumpvars(0, mac_tb);
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clk = 0;
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mtx_payload = 0;
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mtx_start = 0;
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#10;
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for (int i=0; i<32; i=i+1) begin
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mtx_payload = i;
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mtx_start = 0;
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#10;
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mtx_start = 1;
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#10;
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mtx_start = 0;
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while(!mrx_valid) #10;
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#1000;
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assert(mrx_payload == i) else $fatal(0, "data mismatch!");
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end
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$finish();
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end
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endmodule
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`default_nettype wire |