121 lines
2.4 KiB
Systemverilog
121 lines
2.4 KiB
Systemverilog
`default_nettype none
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//`timescale 1ns/1ps
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`define FPGA_MAC 48'h69_69_5A_06_54_91
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`define HOST_MAC 48'h00_E0_4C_68_1E_0C
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`define ETHERTYPE 16'h88_B5
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task send_on_etx_receive_on_mrx (
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input [15:0] data
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);
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ethernet_tx_tb.etx_data = data;
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ethernet_tx_tb.etx_rw = 0;
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ethernet_tx_tb.etx_valid = 0;
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#10;
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ethernet_tx_tb.etx_valid = 1;
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#10;
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ethernet_tx_tb.etx_valid = 0;
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while(!ethernet_tx_tb.mrx_valid) #10;
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$display(ethernet_tx_tb.mrx_payload);
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endtask
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module ethernet_tx_tb();
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// https://www.youtube.com/watch?v=K35qOTQLNpA
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logic clk;
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always begin
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#5;
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clk = !clk;
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end
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logic txen;
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logic [1:0] txd;
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// ethernet tx
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reg [15:0] etx_data;
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reg etx_rw;
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reg etx_valid;
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ethernet_tx #(
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.FPGA_MAC(`FPGA_MAC),
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.HOST_MAC(`HOST_MAC),
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.ETHERTYPE(`ETHERTYPE)
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) etx (
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.clk(clk),
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.data_i(etx_data),
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.rw_i(etx_rw),
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.valid_i(etx_valid),
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.txen(txen),
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.txd(txd));
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// mac_rx, for decoding
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logic crsdv;
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logic [1:0] rxd;
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reg [55:0] mrx_payload;
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reg mrx_valid;
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mac_rx #(
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// this is the host mac since we're using mac_rx to impersonate
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// the host computer, to which packets are currently addressed.
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.FPGA_MAC(`HOST_MAC),
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.ETHERTYPE(`ETHERTYPE)
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) mrx (
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.clk(clk),
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.crsdv(crsdv),
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.rxd(rxd),
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.payload(mrx_payload),
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.valid(mrx_valid));
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logic [15:0] where_ethertype_should_be;
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logic [7:0] where_rw_should_be;
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logic [15:0] where_addr_should_be;
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logic [15:0] where_data_should_be;
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assign {where_ethertype_should_be, where_rw_should_be, where_addr_should_be, where_data_should_be} = mrx_payload;
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assign rxd = txd;
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assign crsdv = txen;
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initial begin
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$dumpfile("ethernet_tx_tb.vcd");
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$dumpvars(0, ethernet_tx_tb);
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clk = 0;
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etx_data = 16'h6970;
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etx_rw = 0;
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etx_valid = 0;
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#50;
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send_on_etx_receive_on_mrx(16'h6970);
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#10000;
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// for (int i=0; i<32; i=i+1) begin
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// mtx_payload = i;
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// mtx_start = 0;
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// #10;
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// mtx_start = 1;
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// #10;
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// mtx_start = 0;
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// while(!mrx_valid) #10;
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// #1000;
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// assert(mrx_payload == i) else $fatal(0, "data mismatch!");
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// end
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$finish();
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end
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endmodule
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`default_nettype wire |