70 lines
1.3 KiB
Systemverilog
70 lines
1.3 KiB
Systemverilog
`default_nettype none
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`timescale 1ns / 1ps
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module ila_tb();
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logic clk;
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logic rst;
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logic rxd;
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logic txd;
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logic probe0, probe1, probe2;
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assign probe0 = count[0];
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assign probe1 = count[1];
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assign probe2 = count[2];
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// ILA
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// later make this a `ILA that gets loaded from a svh file that the python script generates
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ila #(.FIFO_DEPTH(64)) ila(
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.clk(clk),
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.rst(rst),
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.probe0(probe0),
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.probe1(probe1),
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.probe2(probe2),
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.rxd(rxd),
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.txd(txd));
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/* Signal Generator */
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logic [7:0] count = 0;
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always begin
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count = count + 1;
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#10;
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end
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always begin
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#5;
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clk = !clk;
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end
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logic [9:0] uart_data;
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initial begin
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$dumpfile("ila.vcd");
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$dumpvars(0, ila_tb);
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clk = 0;
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rst = 1;
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rxd = 1;
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uart_data = 0;
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#10;
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rst = 0;
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// Wait a little bit to make sure that it doesn't like, explode or something
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#1000;
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// send arm byte!
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uart_data = {1'b1, 8'b00110000, 1'b0};
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for (int i=0; i < 10; i++) begin
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rxd = uart_data[i];
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#8680;
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end
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// see what happens lmao
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#15000000;
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$finish();
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end
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endmodule
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`default_nettype wire
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