71 lines
2.4 KiB
Python
71 lines
2.4 KiB
Python
import json
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import yaml
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from datetime import datetime
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import os
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# this works by taking a template file, parsing it for hooks, and then dropping in our spicy bits of verilog in those hooks.
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# might update this later to just properly instantiate an ILA for us and we do this with parameters, but
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# the fundamental thing i care about is that systemverilog does not live in this file.
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fpath = 'ila.json' # will update for argv soon!
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with open(fpath, 'r') as f:
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config = json.load(f)
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# make sure file is okay
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assert config["probes"]
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assert config["triggers"]
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assert config["uart"] or config["ethernet"] # <- i have ideas hehe
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def splice(source, find, replace):
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# find all instances of find in the source, and replace with replace
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#assert source.count(find) == 1
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return source.replace(find, replace)
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with open('src/ila_template.sv', 'r') as t:
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ila_template = t.read()
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# add timestamp and user
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timestamp = datetime.now().strftime("%d/%m/%Y %H:%M:%S")
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ila_template = splice(ila_template, '@TIMESTAMP', timestamp);
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user = os.environ.get('USER', os.environ.get('USERNAME'))
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ila_template = splice(ila_template, '@USER', user);
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# add trigger
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trigger = [f'({trigger})' for trigger in config['triggers']]
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trigger = ' || '.join(trigger)
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ila_template = splice(ila_template, '@TRIGGER', trigger);
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# add concat
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concat = [name for name in config['probes']]
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concat = ', '.join(concat)
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concat = '{' + concat + '};'
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ila_template = splice(ila_template, '@CONCAT', concat);
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# add probes to ila module definition
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probe_verilog = []
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for name, width in config['probes'].items():
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if width == 1:
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probe_verilog.append(f'input wire {name},')
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else:
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probe_verilog.append(f'input wire [{width-1}:0] {name},')
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probe_verilog = '\n\t'.join(probe_verilog)
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ila_template = splice(ila_template, '@PROBES', probe_verilog);
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# add sample width and depth
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sample_width = sum([width for name, width in config['probes'].items()])
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ila_template = splice(ila_template, '@SAMPLE_WIDTH', str(sample_width))
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ila_template = splice(ila_template, '@SAMPLE_DEPTH', str(config['sample_depth']));
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# add UART configuration
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ila_template = splice(ila_template, '@DATA_WIDTH', str(int(config['uart']['data'])));
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ila_template = splice(ila_template, '@BAUDRATE', str(config['uart']['baudrate']));
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ila_template = splice(ila_template, '@CLK_FREQ_HZ', str(int(config['clock_freq'])));
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# write output file
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with open('src/ila.sv', 'w') as i:
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i.write(ila_template) |