74 lines
2.1 KiB
Python
74 lines
2.1 KiB
Python
from amaranth.sim import Simulator
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from manta.logic_analyzer import LogicAnalyzerFSM
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from manta.utils import *
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"""
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what do we want this to do?
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we want to run a capture in single shot mode, immediate mode, and incremental mode
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single-shot case:
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- exactly the right number of samples are taken
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- we only start taking samples once captured
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immediate case:
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- exactly the right number of samples are taken
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- we only start taking samples once captured
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incremental case:
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- exactly the right number of samples are taken
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- we only take samples when trig is asserted
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"""
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config = {"sample_depth": 8}
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fsm = LogicAnalyzerFSM(config, base_addr=0, interface=None)
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def set_fsm_register(name, data):
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addr = fsm.r.mmap[f"{name}_buf"]["addrs"][0]
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strobe_addr = fsm.r.base_addr
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yield from write_register(fsm, strobe_addr, 0)
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yield from write_register(fsm, addr, data)
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yield from write_register(fsm, strobe_addr, 1)
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yield from write_register(fsm, strobe_addr, 0)
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def test_single_shot_always_trigger():
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def testbench():
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if (yield fsm.r.state != fsm.states["IDLE"]):
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raise ValueError
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yield fsm.trigger.eq(1)
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yield from set_fsm_register("trigger_mode", fsm.trigger_modes["SINGLE_SHOT"])
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yield from set_fsm_register("trigger_location", 4)
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yield from set_fsm_register("request_start", 1)
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yield from set_fsm_register("request_start", 0)
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for _ in range(100):
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yield
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simulate(fsm, testbench, "single_shot_always_trigger.vcd")
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def test_single_shot_wait_to_trigger():
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def testbench():
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if (yield fsm.r.state != fsm.states["IDLE"]):
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raise ValueError
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yield from set_fsm_register("trigger_mode", fsm.trigger_modes["SINGLE_SHOT"])
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yield from set_fsm_register("trigger_location", 4)
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yield from set_fsm_register("request_start", 1)
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yield from set_fsm_register("request_start", 0)
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for _ in range(8):
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yield
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yield fsm.trigger.eq(1)
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for _ in range(100):
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yield
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simulate(fsm, testbench, "single_shot_wait_to_trigger.vcd")
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