281 lines
9.9 KiB
Python
281 lines
9.9 KiB
Python
# Test with 32-bit data/valid/ready/last interface for input, and one for output
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from amaranth import *
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from amaranth.lib.enum import IntEnum
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from manta.utils import *
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class MessageTypes(IntEnum, shape=unsigned(3)):
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READ_REQUEST = 0
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WRITE_REQUEST = 1
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READ_RESPONSE = 2
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WRITE_RESPONSE = 3
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NACK = 4
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class EthernetBridge(Elaboratable):
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def __init__(self):
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self.data_i = Signal(32)
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self.valid_i = Signal()
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self.last_i = Signal()
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self.ready_o = Signal()
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self.data_o = Signal(32)
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self.valid_o = Signal()
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self.last_o = Signal()
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self.ready_i = Signal()
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self.bus_o = Signal(InternalBus())
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self.bus_i = Signal(InternalBus())
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def elaborate(self, platform):
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m = Module()
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seq_num_expected = Signal(13)
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read_len = Signal(7)
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with m.FSM(init="IDLE"):
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with m.State("IDLE"):
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m.d.sync += self.ready_o.eq(1)
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with m.If(self.valid_i):
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# First 32 bits was presented, which contains message type (first 3 bits)
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# as well as sequence number (next 13 bits). The remaining 16 bits are unused.
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# Send NACK if message type or sequence number is incorrect
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with m.If(
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(self.data_i[:3] > max(MessageTypes))
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| (self.data_i[3:16] != seq_num_expected)
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):
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# Wait to NACK if this isn't the last beat in message
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with m.If(~self.last_i):
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m.next = "NACK_WAIT_FOR_LAST"
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# Otherwise, NACK immediately
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with m.Else():
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m.d.sync += self.data_o.eq(
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Cat(MessageTypes.NACK, seq_num_expected)
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)
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m.d.sync += self.valid_o.eq(1)
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m.d.sync += self.last_o.eq(1)
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m.d.sync += self.ready_o.eq(0)
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m.next = "NACK_WAIT_FOR_READY"
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with m.Elif(self.data_i[:3] == MessageTypes.READ_REQUEST):
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m.d.sync += seq_num_expected.eq(seq_num_expected + 1)
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m.d.sync += read_len.eq(self.data_i[16:23] - 1)
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m.d.sync += self.data_o.eq(
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Cat(MessageTypes.READ_RESPONSE, seq_num_expected + 1)
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)
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m.next = "READ_WAIT_FOR_ADDR"
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with m.Elif(self.data_i[:3] == MessageTypes.WRITE_REQUEST):
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m.d.sync += seq_num_expected.eq(seq_num_expected + 1)
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m.next = "WRITE_WAIT_FOR_ADDR"
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with m.State("READ_WAIT_FOR_ADDR"):
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with m.If(self.valid_i):
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# we have the length and the address to read from, let's go!
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m.d.sync += self.bus_o.addr.eq(self.data_i)
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m.d.sync += self.bus_o.data.eq(0)
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m.d.sync += self.bus_o.rw.eq(0)
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m.d.sync += self.bus_o.valid.eq(1)
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with m.If(read_len == 0):
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# we've sent the last read request in this batch to the bus
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m.d.sync += self.bus_o.last.eq(1)
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m.d.sync += read_len.eq(0)
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m.next = "READ"
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with m.State("READ"):
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m.d.sync += self.ready_o.eq(0)
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# Clock out read requests to the bus
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with m.If(read_len > 0):
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m.d.sync += self.bus_o.addr.eq(self.bus_o.addr + 1)
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m.d.sync += read_len.eq(read_len - 1)
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with m.If(read_len == 1):
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m.d.sync += self.bus_o.last.eq(1)
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with m.Else():
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m.d.sync += self.bus_o.eq(
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0
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) # TODO: it's probably overzealous to set the whole bus to zero, but it makes debugging easy so we're doing it xD
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# Clock out any read data from the bus
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with m.If(self.bus_i.valid):
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m.d.sync += self.data_o.eq(self.bus_i.data)
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with m.If(self.bus_i.last):
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m.d.sync += self.last_o.eq(1)
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m.next = "IDLE" # TODO: could save a cycle by checking valid_i to see if there's more work to do
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with m.State("WRITE_WAIT_FOR_ADDR"):
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with m.If(self.valid_i):
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m.d.sync += self.bus_i.addr.eq(self.data_i)
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m.next = "WRITE_FIRST"
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# Don't want to increment address on the first write,
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# and I'm lazy so I'm making a new state to keep track of that
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with m.State("WRITE_FIRST"):
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with m.If(self.valid_i):
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m.d.sync += self.bus_o.data.eq(self.data_i)
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m.d.sync += self.bus_o.rw.eq(1)
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m.d.sync += self.bus_o.valid.eq(1)
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m.d.sync += self.bus_o.last.eq(self.last_i)
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with m.If(self.last_i):
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m.next = "IDLE" # TODO: could save a cycle by checking valid_i to see if there's more work to do
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with m.Else():
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m.next = "WRITE"
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with m.State("WRITE"):
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with m.If(self.valid_i):
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m.d.sync += self.bus_o.addr.eq(self.bus_i.addr + 1)
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m.d.sync += self.bus_o.data.eq(self.data_i)
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m.d.sync += self.bus_o.rw.eq(1)
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m.d.sync += self.bus_o.valid.eq(1)
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m.d.sync += self.bus_o.last.eq(self.last_i)
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with m.Else():
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m.d.sync += self.bus_o.eq(0)
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with m.If(self.bus_o.last):
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m.d.sync += self.bus_o.valid.eq(0)
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m.d.sync += self.bus_o.addr.eq(0)
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m.d.sync += self.bus_o.data.eq(0)
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m.d.sync += self.bus_o.last.eq(0)
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m.d.sync += self.bus_o.rw.eq(0)
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m.next = "IDLE" # TODO: could save a cycle by checking valid_i to see if there's more work to do
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with m.Else():
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m.next = "WRITE"
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with m.State("NACK_WAIT_FOR_LAST"):
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with m.If(self.last_i):
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m.d.sync += self.data_o.eq(Cat(MessageTypes.NACK, seq_num_expected))
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m.d.sync += self.valid_o.eq(1)
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m.d.sync += self.last_o.eq(1)
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m.d.sync += self.ready_o.eq(0)
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m.next = "NACK_WAIT_FOR_READY"
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with m.State("NACK_WAIT_FOR_READY"):
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with m.If(self.ready_i):
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m.d.sync += self.valid_o.eq(0)
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# TODO: remove these next two lines, they're not necessary
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# although they are nice for debug...
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m.d.sync += self.data_o.eq(0)
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m.d.sync += self.last_o.eq(0)
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m.d.sync += self.ready_o.eq(1)
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m.next = "IDLE"
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return m
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# Actual testing below!
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ether_bridge = EthernetBridge()
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from random import randint
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async def send_bytes(ctx, bytes):
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ctx.set(ether_bridge.ready_i, 1)
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ctx.set(ether_bridge.valid_i, 1)
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for i, byte in enumerate(bytes):
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ctx.set(ether_bridge.data_i, byte)
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ctx.set(ether_bridge.last_i, i == len(bytes) - 1)
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while not ctx.get(ether_bridge.ready_o):
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await ctx.tick()
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await ctx.tick()
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ctx.set(ether_bridge.data_i, 0)
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ctx.set(ether_bridge.last_i, 0)
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ctx.set(ether_bridge.valid_i, 0)
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await ctx.tick()
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async def send_bytes_sporadic(ctx, bytes):
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ctx.set(ether_bridge.ready_i, 1)
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ctx.set(ether_bridge.valid_i, 1)
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for i, byte in enumerate(bytes):
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if randint(0, 1):
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ctx.set(ether_bridge.valid_i, 0)
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for _ in range(0, randint(1, 4)):
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await ctx.tick()
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ctx.set(ether_bridge.valid_i, 1)
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ctx.set(ether_bridge.data_i, byte)
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ctx.set(ether_bridge.last_i, i == len(bytes) - 1)
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while not ctx.get(ether_bridge.ready_o):
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await ctx.tick()
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await ctx.tick()
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ctx.set(ether_bridge.data_i, 0)
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ctx.set(ether_bridge.last_i, 0)
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ctx.set(ether_bridge.valid_i, 0)
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await ctx.tick()
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# - type: 3 bits
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# - seq_num: 13 bits
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# - length (only if read request): 7 bits
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async def send_write_request(ctx, seq_num, addr, write_data):
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await send_bytes_sporadic(
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ctx, [(seq_num << 3) | MessageTypes.WRITE_REQUEST, addr] + write_data
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)
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async def send_read_request(ctx, seq_num, addr, read_length):
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await send_bytes_sporadic(
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ctx, [(read_length << 16) | (seq_num << 3) | MessageTypes.READ_REQUEST, addr]
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)
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@simulate(ether_bridge)
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async def test_ether_bridge(ctx):
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await ctx.tick()
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await ctx.tick()
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await ctx.tick()
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# Send a read request with a bad sequence number
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# await send_read_request(ctx, seq_num=1, addr=0, read_length=1)
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# await ctx.tick()
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# await send_read_request(ctx, seq_num=1, addr=1, read_length=1)
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# await ctx.tick()
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# await send_write_request(ctx, seq_num=0, addr=0x1234_5678, write_data=[0x0000_0000, 0x1111_1111, 0x2222_2222])
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# ctx.tick()
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await send_write_request(
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ctx,
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seq_num=0,
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addr=0x1234_5678,
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write_data=[0x0000_0000, 0x1111_1111, 0x2222_2222, 0x3333_3333],
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)
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# await send_write_request(ctx, seq_num=4, addr=0x1234_5678, write_data=[0x0000_0000, 0x1111_1111, 0x2222_2222])
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# await send_read_request(ctx, seq_num=0, addr=0x1234_5678, read_length=10)
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# await send_bytes(ctx, [0x0123_4567])
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# await send_bytes(ctx, [0x0123_4567, 0x89AB_CDEF])
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# await send_bytes(ctx, [0x0123_4567, 0x89AB_CDEF, 0x0123_4567])
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# await send_bytes(ctx, [0x0123_4567, 0x89AB_CDEF, 0x0123_4567, 0x89AB_CDEF])
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ctx.tick()
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for _ in range(20):
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await ctx.tick()
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