124 lines
3.1 KiB
Makefile
124 lines
3.1 KiB
Makefile
# Tool Paths
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VIVADO=/tools/Xilinx/Vivado/2023.1/bin/vivado
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YOSYS=/tools/oss-cad-suite/bin/yosys
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NEXTPNR_ICE40=/tools/oss-cad-suite/bin/nextpnr-ice40
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ICEPACK=/tools/oss-cad-suite/bin/icepack
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test: auto_gen sim formal
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examples: icestick nexys_a7
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clean:
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@echo "Deleting everything matched by .gitignore"
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git clean -Xdf
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serve_docs:
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mkdocs serve
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# Python Operations
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python_build:
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python3 -m build
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pypi_upload: build
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python3 -m twine upload --repository testpypi dist/*
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python_lint:
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python3 -m black src/manta/__init__.py
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python3 -m black src/manta/__main__.py
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# API Generation Tests
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auto_gen:
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python3 test/auto_gen/run_tests.py
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# Build Examples
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NEXYS_A7_EXAMPLES := io_core_ether io_core_uart ps2_logic_analyzer video_sprite_ether video_sprite_uart block_mem_uart logic_analyzer_uart
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.PHONY: nexys_a7 $(NEXYS_A7_EXAMPLES)
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nexys_a7: $(NEXYS_A7_EXAMPLES)
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$(NEXYS_A7_EXAMPLES):
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cd examples/nexys_a7/$@; \
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python3 -m manta gen manta.yaml src/manta.v; \
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rm -rf obj; \
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mkdir -p obj; \
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$(VIVADO) -mode batch \
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-source ../build.tcl \
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-log obj/build.log \
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-jou obj/build.jou; \
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rm -rf .Xil;
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ICESTICK_EXAMPLES := io_core
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.PHONY: icestick $(ICESTICK_EXAMPLES)
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icestick: $(ICESTICK_EXAMPLES)
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$(ICESTICK_EXAMPLES):
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cd examples/icestick/$@; \
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python3 -m manta gen manta.yaml manta.v; \
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$(YOSYS) -p 'synth_ice40 -top top_level -json top_level.json' top_level.sv; \
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$(NEXTPNR_ICE40) --hx1k --json top_level.json --pcf top_level.pcf --asc top_level.asc; \
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$(ICEPACK) top_level.asc top_level.bin; \
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rm -f *.json; \
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rm -f *.asc;
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# Formal Verification
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formal:
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sby -f test/formal_verification/bridge_rx.sby
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# Functional Simulation
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sim: ethernet_tx_tb ethernet_rx_tb mac_tb block_memory_tb io_core_tb logic_analyzer_tb bridge_rx_tb bridge_tx_tb block_memory_tb
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ethernet_tx_tb:
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iverilog -g2012 -o sim.out -y src/manta/ether_iface test/functional_sim/ethernet_tx_tb.sv
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vvp sim.out
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rm sim.out
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ethernet_rx_tb:
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iverilog -g2012 -o sim.out -y src/manta/ether_iface test/functional_sim/ethernet_rx_tb.sv
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vvp sim.out
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rm sim.out
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mac_tb:
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iverilog -g2012 -o sim.out -y src/manta/ether_iface test/functional_sim/mac_tb.sv
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vvp sim.out
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rm sim.out
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block_memory_tb:
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iverilog -g2012 -o sim.out -y src/manta/block_mem_core test/functional_sim/block_memory_tb.sv
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vvp sim.out
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rm sim.out
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io_core_tb:
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iverilog -g2012 -o sim.out -y src/manta \
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test/functional_sim/io_core_tb/io_core_tb.sv \
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test/functional_sim/io_core_tb/io_core.v
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vvp sim.out
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rm sim.out
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logic_analyzer_tb:
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cd test/functional_sim/logic_analyzer_tb; \
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python3 -m manta gen manta.yaml manta.v; \
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iverilog -g2012 -o sim.out logic_analyzer_tb.sv manta.v; \
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vvp sim.out; \
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rm sim.out
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bridge_rx_tb:
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iverilog -g2012 -o sim.out -y src/manta/uart_iface test/functional_sim/bridge_rx_tb.sv
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vvp sim.out
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rm sim.out
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bridge_tx_tb:
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iverilog -g2012 -o sim.out -y src/manta/uart_iface test/functional_sim/bridge_tx_tb.sv
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vvp sim.out
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rm sim.out
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uart_rx_tb:
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iverilog -g2012 -o sim.out -y src/manta/uart_iface test/functional_sim/uart_rx_tb.sv
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vvp sim.out
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rm sim.out
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uart_tx_tb:
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iverilog -g2012 -o sim.out -y src/manta/uart_iface test/functional_sim/uart_tx_tb.sv
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vvp sim.out
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rm sim.out
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