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<h1>Memory Core</h1>
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<h2 id="overview">Overview</h2>
|
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<p>Memory is the de facto means of storing data on FPGAs when the space needed exceeds a few registers. As a result, Manta provides a Memory core, which instantiates a dual-port RAM on the FPGA. One port is provided to the host, and the other is connected to your logic with the standard RAM interface (<code>addr</code>, <code>data_in</code>, <code>data_out</code>, <code>write_enable</code>). This allows the host to provide reasonably large amounts of data to user logic - or the other way around, or a mix of both!</p>
|
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<p>This is a very, very simple task - and while configuration is straightforward, there are a few caveats. More on both topics below:</p>
|
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<h2 id="configuration">Configuration</h2>
|
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<p>Just like the rest of the cores, the Memory core is configured via an entry in a project's configuration file. This is easiest to show by example:</p>
|
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<div class="language-yaml highlight"><pre><span></span><code><span id="__span-0-1"><a id="__codelineno-0-1" name="__codelineno-0-1" href="#__codelineno-0-1"></a><span class="nn">---</span>
|
|
</span><span id="__span-0-2"><a id="__codelineno-0-2" name="__codelineno-0-2" href="#__codelineno-0-2"></a><span class="nt">cores</span><span class="p">:</span>
|
|
</span><span id="__span-0-3"><a id="__codelineno-0-3" name="__codelineno-0-3" href="#__codelineno-0-3"></a><span class="w"> </span><span class="nt">my_memory</span><span class="p">:</span>
|
|
</span><span id="__span-0-4"><a id="__codelineno-0-4" name="__codelineno-0-4" href="#__codelineno-0-4"></a><span class="w"> </span><span class="nt">type</span><span class="p">:</span><span class="w"> </span><span class="l l-Scalar l-Scalar-Plain">memory</span>
|
|
</span><span id="__span-0-5"><a id="__codelineno-0-5" name="__codelineno-0-5" href="#__codelineno-0-5"></a><span class="w"> </span><span class="nt">mode</span><span class="p">:</span><span class="w"> </span><span class="l l-Scalar l-Scalar-Plain">bidirectional</span>
|
|
</span><span id="__span-0-6"><a id="__codelineno-0-6" name="__codelineno-0-6" href="#__codelineno-0-6"></a><span class="w"> </span><span class="nt">width</span><span class="p">:</span><span class="w"> </span><span class="l l-Scalar l-Scalar-Plain">12</span>
|
|
</span><span id="__span-0-7"><a id="__codelineno-0-7" name="__codelineno-0-7" href="#__codelineno-0-7"></a><span class="w"> </span><span class="nt">depth</span><span class="p">:</span><span class="w"> </span><span class="l l-Scalar l-Scalar-Plain">16384</span>
|
|
</span></code></pre></div>
|
|
<p>There's a few parameters that get configured here, including:</p>
|
|
<ul>
|
|
<li><code>name</code>: The name of the Memory core. This name is used to reference the core when working with the API, and can be whatever you'd like.</li>
|
|
<li><code>type</code>: This denotes that this is a Memory core. All cores contain a <code>type</code> field, which must be set to <code>memory</code> to be recognized as an Memory core.</li>
|
|
<li><code>mode</code>: The mode for the Memory core to operate in. This must be one of <code>bidirectional</code>, <code>host_to_fpga</code>, or <code>fpga_to_host</code>. Bidirectional memories can be both read or written to by the host and FPGA, but they require the use of a True Dual Port RAM, which is not available on all platforms (most notably, the ice40). Host-to-fpga and fpga-to-host RAMs only require a Simple Dual Port RAM, which is available on nearly all platforms.</li>
|
|
<li><code>width</code>: The width of the Memory core, in bits.</li>
|
|
<li><code>depth</code>: The depth of the Memory core, in entries.</li>
|
|
</ul>
|
|
<p>Manta won't impose any limit on the width or depth of the memory you instantiate, but since Manta instantiates BRAM primitives on the FPGA, you will be limited by what your FPGA can support. It helps to know your particular FPGA's architecture here.</p>
|
|
<h3 id="on-chip-implementation">On-Chip Implementation</h3>
|
|
<p>For most use cases, Manta will choose to implement the memory in Block RAM, if it is available on the device. However, the Verilog produced by Manta may be inferred to a number of memory types, including FF RAM or LUT (Distributed) RAM. For more information on how this is chosen, please refer to the <a href="https://yosyshq.readthedocs.io/projects/yosys/en/latest/CHAPTER_Memorymap.html">Yosys documentation</a>.</p>
|
|
<h3 id="python-api">Python API</h3>
|
|
<p>The Memory core functionality is stored in the <code>Manta.MemoryCore</code> classes in <a href="https://github.com/fischermoseley/manta/blob/main/src/manta/memory_core.py">src/manta/memory_core.py</a>, and it may be controlled with the two functions:</p>
|
|
<p>Just like with the other cores, interfacing with the Memory with the Python API is simple:</p>
|
|
<div class="language-python highlight"><pre><span></span><code><span id="__span-1-1"><a id="__codelineno-1-1" name="__codelineno-1-1" href="#__codelineno-1-1"></a><span class="kn">from</span> <span class="nn">manta</span> <span class="kn">import</span> <span class="n">Manta</span>
|
|
</span><span id="__span-1-2"><a id="__codelineno-1-2" name="__codelineno-1-2" href="#__codelineno-1-2"></a><span class="n">m</span> <span class="o">=</span> <span class="n">manta</span><span class="p">(</span><span class="s1">'manta.yaml'</span><span class="p">)</span>
|
|
</span><span id="__span-1-3"><a id="__codelineno-1-3" name="__codelineno-1-3" href="#__codelineno-1-3"></a>
|
|
</span><span id="__span-1-4"><a id="__codelineno-1-4" name="__codelineno-1-4" href="#__codelineno-1-4"></a><span class="n">m</span><span class="o">.</span><span class="n">my_memory</span><span class="o">.</span><span class="n">write</span><span class="p">(</span><span class="n">addr</span><span class="o">=</span><span class="mi">38</span><span class="p">,</span> <span class="n">data</span><span class="o">=</span><span class="mi">600</span><span class="p">)</span>
|
|
</span><span id="__span-1-5"><a id="__codelineno-1-5" name="__codelineno-1-5" href="#__codelineno-1-5"></a><span class="n">m</span><span class="o">.</span><span class="n">my_memory</span><span class="o">.</span><span class="n">write</span><span class="p">(</span><span class="n">addr</span><span class="o">=</span><span class="mh">0x1234</span><span class="p">,</span> <span class="n">data</span> <span class="o">=</span> <span class="mb">0b100011101011</span><span class="p">)</span>
|
|
</span><span id="__span-1-6"><a id="__codelineno-1-6" name="__codelineno-1-6" href="#__codelineno-1-6"></a><span class="n">m</span><span class="o">.</span><span class="n">my_memory</span><span class="o">.</span><span class="n">write</span><span class="p">(</span><span class="mh">0x0612</span><span class="p">,</span> <span class="mh">0x2001</span><span class="p">)</span>
|
|
</span><span id="__span-1-7"><a id="__codelineno-1-7" name="__codelineno-1-7" href="#__codelineno-1-7"></a>
|
|
</span><span id="__span-1-8"><a id="__codelineno-1-8" name="__codelineno-1-8" href="#__codelineno-1-8"></a><span class="n">foo</span> <span class="o">=</span> <span class="n">m</span><span class="o">.</span><span class="n">my_memory</span><span class="o">.</span><span class="n">write</span><span class="p">(</span><span class="n">addr</span><span class="o">=</span><span class="mi">38</span><span class="p">)</span>
|
|
</span><span id="__span-1-9"><a id="__codelineno-1-9" name="__codelineno-1-9" href="#__codelineno-1-9"></a><span class="n">foo</span> <span class="o">=</span> <span class="n">m</span><span class="o">.</span><span class="n">my_memory</span><span class="o">.</span><span class="n">write</span><span class="p">(</span><span class="n">addr</span><span class="o">=</span><span class="mi">1234</span><span class="p">)</span>
|
|
</span><span id="__span-1-10"><a id="__codelineno-1-10" name="__codelineno-1-10" href="#__codelineno-1-10"></a><span class="n">foo</span> <span class="o">=</span> <span class="n">m</span><span class="o">.</span><span class="n">my_memory</span><span class="o">.</span><span class="n">write</span><span class="p">(</span><span class="mh">0x0612</span><span class="p">)</span>
|
|
</span></code></pre></div>
|
|
<p>Reading/writing in batches is also supported. This is recommended where possible, as reads are massively sped up by performing them in bulk:</p>
|
|
<div class="language-python highlight"><pre><span></span><code><span id="__span-2-1"><a id="__codelineno-2-1" name="__codelineno-2-1" href="#__codelineno-2-1"></a><span class="n">addrs</span> <span class="o">=</span> <span class="nb">list</span><span class="p">(</span><span class="nb">range</span><span class="p">(</span><span class="mi">0</span><span class="p">,</span> <span class="mi">1234</span><span class="p">))</span>
|
|
</span><span id="__span-2-2"><a id="__codelineno-2-2" name="__codelineno-2-2" href="#__codelineno-2-2"></a><span class="n">datas</span> <span class="o">=</span> <span class="nb">list</span><span class="p">(</span><span class="nb">range</span><span class="p">(</span><span class="mi">1234</span><span class="p">,</span> <span class="mi">2468</span><span class="p">))</span>
|
|
</span><span id="__span-2-3"><a id="__codelineno-2-3" name="__codelineno-2-3" href="#__codelineno-2-3"></a><span class="n">m</span><span class="o">.</span><span class="n">my_memory</span><span class="o">.</span><span class="n">write</span><span class="p">(</span><span class="n">addrs</span><span class="p">,</span> <span class="n">datas</span><span class="p">)</span>
|
|
</span><span id="__span-2-4"><a id="__codelineno-2-4" name="__codelineno-2-4" href="#__codelineno-2-4"></a>
|
|
</span><span id="__span-2-5"><a id="__codelineno-2-5" name="__codelineno-2-5" href="#__codelineno-2-5"></a><span class="n">foo</span> <span class="o">=</span> <span class="n">m</span><span class="o">.</span><span class="n">my_memory</span><span class="o">.</span><span class="n">read</span><span class="p">(</span><span class="n">addrs</span><span class="p">)</span>
|
|
</span></code></pre></div>
|
|
<h3 id="synchronicity">Synchronicity</h3>
|
|
<p>Since Manta's <a href="../architecture/#data-bus">data bus</a> is only 16-bits wide, it's only possible to manipulate the Memory core in 16-bit increments. This means that if you have a RAM that's ≤16 bits wide, you'll only need to issue a single bus transaction to read/write one entry in the RAM. However, if you have a RAM that's ≥16 bits wide, you'll need to issue a bus transaction to update each 16-bit slice of it. For instance, updating a single entry in a 33-bit wide RAM would require sending 3 messages to the FPGA: one for bits 1-16, another for bits 17-32, and one for bit 33. If your application expects each RAM entry to update instantaneously, this could be problematic.</p>
|
|
<p>There's a few different ways to solve this - you could use an IO core to signal when a RAM's contents or valid - or you could ping-pong between two RAMs while one is being modified. The choice is yours, and Manta makes no attempt to prescribe any particular approach.</p>
|
|
<p>Lastly, the interface you use (and to a lesser extent, your operating system) will determine the space between bus transactions. For instance, 100Mbit Ethernet is a thousand times faster than 115200bps UART, so the time where the RAM is invalid is a thousand times smaller.</p>
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