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manta/examples/nexys_a7/lut_ram_ether
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Fischer Moseley 54b97fd120 add working ethernet verilog autogeneration woot woot :) 2023-04-28 14:57:36 -04:00
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divider.sv tidy examples 2023-04-28 14:57:36 -04:00
manta.yaml add working ethernet verilog autogeneration woot woot :) 2023-04-28 14:57:36 -04:00
read_write_test.py add working ethernet verilog autogeneration woot woot :) 2023-04-28 14:57:36 -04:00
ssd.v tidy examples 2023-04-28 14:57:36 -04:00
top_level.sv add working ethernet verilog autogeneration woot woot :) 2023-04-28 14:57:36 -04:00
top_level.xdc add working ethernet verilog autogeneration woot woot :) 2023-04-28 14:57:36 -04:00