113 lines
1.6 KiB
Systemverilog
113 lines
1.6 KiB
Systemverilog
`default_nettype none
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`timescale 1ns / 1ps
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`define CP 10
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`define HCP 5
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module uart_tx_tb();
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logic clk;
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logic [7:0] tb_utx_data;
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logic tb_utx_valid;
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logic utx_tb_busy;
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logic utx_tb_tx;
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uart_tx #(.CLOCKS_PER_BAUD(10)) utx (
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.clk(clk),
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.data(tb_utx_data),
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.valid(tb_utx_valid),
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.busy(utx_tb_busy),
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.tx(utx_tb_tx));
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logic zcpu_tb_tx;
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logic zcpu_tb_busy;
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tx_uart #(.CLOCKS_PER_BAUD(10)) zcpu_utx (
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.i_clk(clk),
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.i_wr(tb_utx_valid),
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.i_data(tb_utx_data),
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.o_uart_tx(zcpu_tb_tx),
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.o_busy(zcpu_tb_busy));
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logic zcpu_urx_valid;
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logic[7:0] zcpu_urx_data;
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rx_uart #(.CLOCKS_PER_BAUD(10)) zcpu_urx (
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.i_clk(clk),
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.i_uart_rx(utx_tb_tx),
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.o_wr(zcpu_urx_valid),
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.o_data(zcpu_urx_data));
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always begin
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#`HCP
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clk = !clk;
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end
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initial begin
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$dumpfile("uart_tx.vcd");
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$dumpvars(0, uart_tx_tb);
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clk = 0;
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tb_utx_data = 0;
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tb_utx_valid = 0;
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#`HCP;
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#(10*`CP);
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$display("send a byte");
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tb_utx_data = 8'h69;
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tb_utx_valid = 1;
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#`CP;
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tb_utx_valid = 0;
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#(150*`CP);
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$display("send another byte");
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tb_utx_data = 8'h42;
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tb_utx_valid = 1;
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#`CP;
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tb_utx_valid = 0;
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#(150*`CP);
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$display("send two bytes back to back");
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tb_utx_data = 8'h69;
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tb_utx_valid = 1;
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#`CP;
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tb_utx_valid = 0;
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#(99*`CP);
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tb_utx_data = 8'h42;
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tb_utx_valid = 1;
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#`CP;
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tb_utx_valid = 0;
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#(150*`CP);
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$display("send two bytes back to back, but keep valid asserted");
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tb_utx_data = 8'h69;
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tb_utx_valid = 1;
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#`CP;
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#(99*`CP);
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tb_utx_data = 8'h42;
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tb_utx_valid = 1;
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#`CP;
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tb_utx_valid = 0;
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#(150*`CP);
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$finish();
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end
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endmodule
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`default_nettype wire
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