77 lines
2.5 KiB
Python
77 lines
2.5 KiB
Python
from amaranth import *
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from amaranth.lib import io
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from manta import *
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from time import sleep
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class UARTLogicAnalyzerExample(Elaboratable):
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def __init__(self, platform, port):
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self.platform = platform
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# Create Manta instance
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self.manta = Manta()
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# Configure it to communicate over Ethernet
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self.manta.interface = UARTInterface(
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port=port,
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baudrate=2000000,
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clock_freq=platform.default_clk_frequency,
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)
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self.probe0 = Signal(1)
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self.probe1 = Signal(2)
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self.probe2 = Signal(3)
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self.probe3 = Signal(4)
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self.manta.cores.la = LogicAnalyzerCore(
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sample_depth=2048,
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probes=[self.probe0, self.probe1, self.probe2, self.probe3],
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)
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def elaborate(self, platform):
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m = Module()
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# Add Manta as a submodule
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m.submodules.manta = self.manta
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counter = Signal(10)
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m.d.sync += counter.eq(counter + 1)
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m.d.comb += self.probe0.eq(counter[0])
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m.d.comb += self.probe1.eq(counter[1:2])
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m.d.comb += self.probe2.eq(counter[3:5])
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m.d.comb += self.probe3.eq(counter[6:])
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# Wire UART pins to the Manta instance
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uart_pins = platform.request("uart", dir={"tx": "-", "rx": "-"})
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m.submodules.uart_rx = uart_rx = io.Buffer("i", uart_pins.rx)
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m.submodules.uart_tx = uart_tx = io.Buffer("o", uart_pins.tx)
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m.d.comb += self.manta.interface.rx.eq(uart_rx.i)
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m.d.comb += uart_tx.o.eq(self.manta.interface.tx)
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return m
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def test(self):
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# Build and program the FPGA
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self.platform.build(self, do_program=True)
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# Take a capture
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self.manta.cores.la.trigger_mode = TriggerModes.IMMEDIATE
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cap = self.manta.cores.la.capture()
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cap.export_vcd("capture.vcd")
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cap.export_csv("capture.csv")
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cap.export_playback_verilog("capture.v")
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# Amaranth has a built-in build system, and well as a set of platform
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# definitions for a huge number of FPGA boards. The class defined above is
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# very generic, as it specifies a design independent of any particular FGPA
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# board. This means that by changing which platform you pass UARTIOCoreExample
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# below, you can port this example to any FPGA board!
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from amaranth_boards.icestick import ICEStickPlatform
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UARTLogicAnalyzerExample(
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platform=ICEStickPlatform(),
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port="/dev/serial/by-id/usb-Lattice_Lattice_FTUSB_Interface_Cable-if01-port0",
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).test()
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