61 lines
2.1 KiB
Python
61 lines
2.1 KiB
Python
import os
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import subprocess
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import sys
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import pytest
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verilog_root_dirs = [
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"examples/verilog/icestick/uart_io_core",
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"examples/verilog/icestick/uart_logic_analyzer",
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"examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core",
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"examples/verilog/nexys4_ddr/uart_host_to_fpga_mem",
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"examples/verilog/nexys4_ddr/uart_io_core",
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"examples/verilog/nexys4_ddr/uart_logic_analyzer",
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]
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@pytest.mark.parametrize("root_dir", verilog_root_dirs)
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def test_verilog_examples_build(root_dir):
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result = subprocess.run(
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["./build.sh"], cwd=root_dir, capture_output=True, text=True
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)
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if result.returncode != 0:
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raise ValueError(f"Command failed with return code {result.returncode}.")
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# Patch the PATH variable so imports from examples/ are possible
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parent_dir = os.path.abspath(os.path.join(os.path.dirname(__file__), ".."))
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sys.path.insert(0, parent_dir)
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# Import Platforms
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from amaranth_boards.icestick import ICEStickPlatform
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from amaranth_boards.nexys4ddr import Nexys4DDRPlatform
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# Import Examples
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from examples.amaranth.ethernet_io_core import EthernetIOCoreExample
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from examples.amaranth.uart_io_core import UARTIOCoreExample
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from examples.amaranth.uart_logic_analyzer import UARTLogicAnalyzerExample
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from examples.amaranth.uart_memory_core import UARTMemoryCoreExample
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# Manually specify a list of examples/platforms to test.
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# This is necessary as some examples don't work without some amount of onboard
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# IO - for instance, the UARTMemoryCore example requires switches and LEDs to
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# read out the memory provided by Manta, but the Icestick doesn't have any
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# switches.
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amaranth_examples_cases = [
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(UARTIOCoreExample, ICEStickPlatform),
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(UARTIOCoreExample, Nexys4DDRPlatform),
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(UARTLogicAnalyzerExample, ICEStickPlatform),
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(UARTLogicAnalyzerExample, Nexys4DDRPlatform),
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(UARTMemoryCoreExample, Nexys4DDRPlatform),
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(EthernetIOCoreExample, Nexys4DDRPlatform),
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]
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@pytest.mark.parametrize("example, platform", amaranth_examples_cases)
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def test_amaranth_examples_build(example, platform):
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design = example(platform(), port="auto")
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design.platform.build(design, do_program=False)
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